TFT Array Substrate with Merged Gate and Capacitor Electrodes
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Solution Overview
Problem
The manufacturing process of flat panel display devices, such as organic light-emitting display devices, is complex and costly due to the need for intricate patterning of thin film transistors (TFTs), capacitors, and wiring, which increases the cost and time required for mask preparation and photolithography steps.
Innovation Solution
A TFT array substrate is designed with a specific layer structure that includes a first insulating layer under the lower electrode, a second insulating layer between the gate electrode and source/drain electrodes, and a third insulating layer with a higher dielectric constant than the first, allowing for simpler manufacturing with fewer mask processes and improved signal transmission characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography with masks is used to form fine patterns of TFTs, capacitors, and wiring, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The gate electrode and lower electrode are merged into the same conductive layer and patterned simultaneously using a single mask, eliminating the need for separate patterning steps. The first insulating layer serves dual functions as both the gate insulator and the capacitor dielectric layer, reducing the total number of layers and manufacturing steps while maintaining precise pattern formation through photolithography
2Manufacturing precision
If multiple insulating layers are used in the capacitor structure, then manufacturing precision is improved, but manufacturing time and cost increase
Solution Approach 1:
The first insulating layer is formed as a single layer that simultaneously serves as the gate insulator between the gate electrode and active layer, and as the capacitor dielectric between the lower electrode and upper electrode. This merging of functions reduces the number of insulating layers from multiple separate layers to a single integrated layer, decreasing manufacturing cycle time while maintaining precise layer alignment through standard photolithography processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing complexity and cost by allowing for a simpler process with fewer mask steps, while enhancing signal transmission and increasing the aperture ratio of the organic light-emitting display device through optimized dielectric and conductive layer design.
Implementation Method 1
A third insulating layer is disposed on the second insulating layer and an upper electrode of the capacitor is disposed on the third insulating layer... A dielectric constant of the third insulating layer may be higher than a dielectric constant of the first insulating layer
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
A thin film transistor (TFT) array substrate includes a TFT on a substrate, the TFT including an active layer (212), gate electrode (214), source electrode (218a), drain electrode (218b), first insulating layer (13) between the active layer and the gate electrode, and second insulating layer (15) between the gate electrode and the source and drain electrodes; a pixel electrode (117) on the first insulating layer and the second insulating layer, the pixel electrode being connected to one of the source electrode and drain electrode; a capacitor including a lower electrode (314) on a same layer as the gate electrode and an upper electrode (317) including the same material as the pixel electrode; a third insulating layer (116, 316) directly between the second insulating layer and the pixel electrode and between the lower electrode and the upper electrode; and a fourth insulating layer (19) covering the source electrode, the drain electrode, and the upper electrode, and exposing the pixel electrode.