Synapse Memory Device Fabrication for Low-Voltage Multi-Level Storage
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Solution Overview
Problem
Conventional charge trap flash memory devices require high operating voltages and lack multi-level memory capabilities, limiting their efficiency and integration in neuromorphic applications.
Innovation Solution
A synapse memory device is fabricated using a method that includes forming specific regions on a substrate, such as source, drain, and channel regions, with a charge trap layer and threshold switching layer, allowing for low-voltage operation and multi-level memory functionality by controlling charge storage and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional charge trap flash memory structure is used, then high integration and compatibility with existing semiconductor processes are achieved, but high operating voltage is required and multi-level memory capabilities are lacking
Solution Approach 1:
The memory device is divided into two distinct transistors: a first transistor with a memory layer for charge storage and a second transistor without a memory layer for control. This segmentation allows the first transistor to provide multi-level memory capability through charge trapping while the second transistor enables low-voltage operation by controlling current flow, thus resolving the contradiction between multi-level capability and low operating voltage
Solution Approach 2:
The memory layer is constructed as a composite structure including a charge trap layer (e.g., Si3N4) and a threshold switching layer (e.g., NiO, TaO, or TiO2). The charge trap layer provides multi-level storage capability while the threshold switching layer enables low-voltage operation by switching between high-resistance and low-resistance states, thereby achieving both multi-level memory capability and reduced operating voltage
2Reliability
If conventional charge trap flash memory is used, then non-volatile memory functionality is achieved, but current leakage is high and device lifespan is limited
Solution Approach 1:
The threshold switching layer acts as an intermediary between the charge trap layer and the channel region. It controls current flow by switching between high-resistance (off-state) and low-resistance (on-state) conditions, thereby reducing current leakage during non-volatile storage while allowing controlled charge injection and extraction, which extends device lifespan
Solution Approach 2:
The threshold switching layer dynamically changes its resistance parameter based on applied voltage. At low voltages, it maintains high resistance to prevent current leakage and preserve stored charge. At higher voltages, it switches to low resistance to allow charge injection for programming or extraction for erasing, thus reducing energy loss and improving reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The synapse memory device operates at low voltages below 20 V, enabling efficient multi-level memory storage with reduced current leakage and extended device lifespan, suitable for neuromorphic networks.
Implementation Method 1
A charge trap flash (CTF) memory, which is a type of the flash memory, stores or deletes information by storing a charge in a charge trap layer, or removing the charge stored in the charge trap layer, by using a charge tunneling effect.
Implementation Method 2
forming a first source region, a source-drain shared area, and a drain region by implanting a first conductivity-type dopant in regions of a substrate spaced apart from each other
Data Source
AI summary
Example embodiments relate to a method of fabricating a synapse memory device capable of being driven at a low voltage and realizing a multi-level memory. The synapse memory device includes a two-transistor structure in which a drain region of a first transistor including a memory layer and a first source region of a second transistor share a source-drain shared area. The synapse memory device is controlled by applying a voltage through the source-drain shared area. The memory layer includes a charge trap layer and a threshold switching layer, and may realize a non-volatile multi-level memory function.