Semiconductor Memory Device Layered Structure Optimization
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in maintaining reliable read operations due to variations in the dimensions of semiconductor layers and word line pillars, which affect the resistance and current flow, leading to potential decreases in data storage and retrieval efficiency.
Innovation Solution
The semiconductor memory device is designed with a configuration where the thickness and width of semiconductor layers and word line pillars vary systematically, with thicker layers and narrower conductive layers on the lower layers and thinner layers and wider conductive layers on the upper layers, optimizing the channel length and resistance between memory cell transistors to enhance current flow and operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform thickness and width are used for semiconductor layers and word line pillars across all layers, then manufacturing is simpler, but resistance varies due to dimensional variations affecting current flow and operational reliability
Solution Approach 1:
The patent applies local quality by making the thickness of semiconductor layers and the width of word line pillars vary according to their vertical position in the stack. Specifically, lower layers have greater thickness/width than upper layers, optimizing current flow and resistance characteristics for each layer's specific operational requirements rather than using uniform dimensions throughout.
Solution Approach 2:
The patent implements dynamics by creating a progressive gradient in dimensional parameters across layers. The thickness and width systematically decrease from lower to upper layers, allowing the structure to adapt its electrical characteristics dynamically across different vertical positions to maintain consistent current flow and resistance throughout the three-dimensional memory array.
2Reliability
If thicker semiconductor layers and narrower conductive layers are used on lower layers, then current flow and resistance are optimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by systematically varying the thickness and width parameters of semiconductor layers and word line pillars across different vertical layers. Lower layers are formed with greater thickness and width, while upper layers have reduced dimensions, creating an optimized gradient that improves read operation reliability by maintaining consistent current flow and resistance characteristics throughout the memory array.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes first and second semiconductor layers and a first conductive layer. The first and second semiconductor layers extend in a first direction. The second semiconductor layer is stacked above the first semiconductor layer in a second direction intersecting the first direction. The first conductive layer intersects the first and second semiconductor layers and extends in the second direction. The first conductive layer includes first and second portions intersecting the first and second semiconductor layers respectively. A width of the first portion in the first direction is smaller than a width of the second portion in the first direction. A thickness of the first semiconductor layer in the second direction is larger than a thickness of the second semiconductor layer in the second direction.