Negative Capacitance FinFET Hysteresis Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing power density of integrated circuits limits their growth, and ferroelectric negative capacitors face challenges in reducing the hysteresis window for effective switching in logic applications, which affects the subthreshold slope and efficiency of CMOS devices.
Innovation Solution
A negative capacitance FinFET device is developed with a ferroelectric negative capacitor connected to the gate stack, where the extension length from the gate stack to the drain or source electrode is optimized to reduce the hysteresis window to 1 V or less, using materials like La0.7Sr0.3MnO3, PVDF, and PbZrTiO3, achieving a subthreshold slope of 5 mV/decade to 20 mV/decade at room temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ferroelectric negative capacitor is used to achieve subthreshold slope below 60 mV/decade, then switching efficiency is improved, but hysteresis window increases
Solution Approach 1:
The patent changes the physical parameters of the device by introducing a specific extension length (Lext) of 80-150 nm from the gate stack sidewall to the drain/source electrode. This parameter modification reduces the hysteresis window to 1V or less while preserving the negative capacitance effect that enables sub-60mV/decade subthreshold slope, thus resolving the contradiction between switching efficiency and hysteresis reduction
Solution Approach 2:
The patent applies local quality by creating a specific structural region (the extension length area) with distinct electrical characteristics. This localized structural modification affects only the critical region near the gate stack, allowing hysteresis reduction without compromising the overall negative capacitance functionality in other regions of the device
2Object-generated harmful factors
If extension length is increased to reduce hysteresis, then hysteresis window decreases, but device area increases
Solution Approach 1:
The patent applies partial action by extending the electrode only partially (80-150 nm) from the gate stack sidewall rather than across the entire device. This limited extension is sufficient to reduce hysteresis to 1V or less without unnecessarily increasing the overall device area, achieving the desired effect with minimal dimensional increase
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the switching speed and reduces hysteresis, allowing for low-power operation and voltage amplification, effectively addressing the limitations of conventional CMOS devices by achieving a subthreshold slope below the physical limit of 60 mV/decade.
Implementation Method 1
the negative capacitance in the ferroelectric negative capacitor is explicitly revealed by phase transition from an initial polarization state to an alternate state caused by the movement of the dipoles inside the ferroelectric layer
Implementation Method 2
ferroelectric materials for CMOS applications have also been proposed, and negative capacitance in ferroelectric capacitors formed of the ferroelectric materials has been experimentally demonstrated
Implementation Method 3
a ferroelectric negative capacitor connected to the gate stack of the FinFET device and having a negative capacitance
Data Source
AI summary
Provided is a negative capacitance FinFET device including a FinFET device including a gate stack, a drain electrode and a source electrode formed on a substrate and a ferroelectric negative capacitor connected to the gate stack of the FinFET device and having a negative capacitance. The FinFET device has an extension length (Lext) from a side-wall of the gate stack to the drain electrode or the source electrode and the extension length is set such that a size of a hysteresis window in the negative capacitance FinFET device is 1 V or less.