Gate Bus Line Oscillation Suppression via Local Width Reduction

Solution Overview

Problem

Existing semiconductor devices require epi or chip resistors to suppress loop oscillations of odd mode, which either increase component count or lead to gate leak currents due to large resistor areas, and are ineffective at achieving the necessary low resistance for suppression.

Innovation Solution

A semiconductor device manufacturing method involving a metal layer with a patterned gate bus line having a small width portion to achieve high resistance without the need for epi or chip resistors, using a plated layer and mask layers to accurately control the resistance and pattern the gate bus line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an epi resistor is electrically coupled between gate pads to suppress loop oscillation, then oscillation suppression is achieved, but the resistor area becomes large causing gate leak current

Engineering Contradiction:

Improveloop oscillation suppressionVSAvoidgate leak current

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The gate bus line width is locally reduced at specific positions between adjacent gate fingers to create high resistance sections. This local geometry change provides the necessary resistance for oscillation suppression without requiring large-area epi resistors, thereby avoiding gate leak current while achieving the same functional effect.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The resistance of the gate bus line is adjusted by changing its geometric parameters (width and length) rather than using a separate resistor component. By reducing the width and increasing the length of specific gate bus line sections, the resistance is increased to provide oscillation suppression without the harmful effects of epi resistors.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If a chip resistor is electrically coupled between gate pads to suppress loop oscillation, then oscillation suppression is achieved, but the component count increases

Engineering Contradiction:

Improveloop oscillation suppressionVSAvoidcomponent count

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The oscillation suppression function is merged into the gate bus line structure itself by creating high resistance sections through width reduction. This integrates the suppression function into the existing interconnect structure, eliminating the need for separate chip resistor components and reducing overall device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The gate bus line serves multiple functions: it provides electrical connection between gate fingers and simultaneously provides oscillation suppression through its high resistance sections. This multi-functionality eliminates the need for dedicated suppression components, reducing component count while maintaining the suppression effect.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If an epi resistor is used to suppress loop oscillation, then oscillation suppression is achieved, but the resistance is insufficient for effective suppression

Engineering Contradiction:

Improveloop oscillation suppressionVSAvoidresistance control

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The gate bus line width is locally reduced at specific positions between adjacent gate fingers to create high resistance sections. This local geometry change provides the necessary resistance for oscillation suppression without requiring large-area epi resistors, thereby avoiding gate leak current while achieving the same functional effect.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The resistance of the gate bus line is adjusted by changing its geometric parameters (width and length) rather than using a separate resistor component. By reducing the width and increasing the length of specific gate bus line sections, the resistance is increased to provide oscillation suppression without the harmful effects of epi resistors.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively suppresses loop oscillations of odd mode without increasing component count or causing gate leak currents, maintaining gain characteristic and phase balance while reducing capacitance and component complexity.

Implementation Method 1

forming a plated layer having a pattern corresponding to a pattern of a gate bus line which couples each gate finger of a plurality of FETs on the metal layer

Methodology Applied

Scientific EffectElectroplating: Electroplating

Data Source

PatentUS9196492B2Method for manufacturing semiconductor device

Publication Date: 2015.11.24 SUMITOMO ELECTRIC DEVICE INNOVATIONS

AI summary

A method for manufacturing a semiconductor device includes: forming a metal layer on a semiconductor layer; forming a plated layer having a pattern corresponding to a pattern of a gate bus line which couples each gate finger of a plurality of FETs on the metal layer, the pattern corresponding to the pattern of the gate bus line having a deficient part; forming a mask layer which covers the metal layer exposed in the deficient part; and patterning the metal layer by using the plated layer and the mask layer as a mask.