Electro-optical Device Gate Insulating Layer Thickness
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Solution Overview
Problem
Existing electro-optical devices with reduced dielectric layer thickness in storage capacitors face issues of reduced dielectric strength and dielectric breakdown due to nonuniform electric fields and morphology-dependent deposition, leading to reduced capacitance and reliability.
Innovation Solution
The electro-optical device incorporates a gate insulating layer with thin portions for high capacitance and thick portions to mitigate electric field concentration, ensuring high dielectric strength by using a two-layer structure with a lower and upper gate insulating sublayer, where the upper sublayer forms the dielectric layers without exposure to etching, maintaining clean interfaces and preventing pinholes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of dielectric layers in storage capacitors is reduced to increase capacitance per unit area, then the capacitance per unit area increases and aperture ratio increases, but the dielectric strength is reduced and dielectric breakdown occurs
Solution Approach 1:
The gate insulating layer is designed with different thicknesses in different regions: thin portions (50-150 nm) in the inner portions of overlapping regions between lower and upper electrodes to increase capacitance, and thick portions (200-500 nm) in regions overlapping with end portions of lower electrodes to maintain dielectric strength and prevent breakdown. This local differentiation resolves the contradiction between maximizing capacitance and maintaining reliability.
2Quantity of substance
If the gate insulating layer is etched to form thin portions for storage capacitors, then the dielectric layer thickness is reduced for high capacitance, but etching-related defects such as pinholes and nonuniform regions are introduced
Solution Approach 1:
The gate insulating layer is segmented into two distinct sublayers: a first gate insulating sublayer (200-500 nm) that is etched to form thin portions, and a second gate insulating sublayer (50-150 nm) that is formed subsequently without etching. This segmentation allows the first sublayer to provide the thin dielectric regions for high capacitance while the second sublayer provides a clean, defect-free interface for the upper electrode, eliminating etching-related defects in the final dielectric structure.
3Reliability
If the thickness of gate insulating layers is increased to maintain dielectric strength, then the dielectric strength is maintained, but the capacitance per unit area of storage capacitors is reduced
Solution Approach 1:
The gate insulating layer structure provides thick portions (200-500 nm) in regions overlapping with end portions of lower electrodes to maintain dielectric strength and prevent breakdown, while providing thin portions (50-150 nm) in inner portions of overlapping regions between lower and upper electrodes to maximize capacitance per unit area. This local differentiation allows simultaneous optimization of both dielectric strength and capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances capacitance per unit area, maintains high dielectric strength, and increases the aperture ratio of pixels while preventing dielectric breakdown and reducing etching-related defects.
Implementation Method 1
when voltages are applied between the lower and upper electrodes, electric fields cannot be uniformly generated across the dielectric layers and therefore are concentrated on the end portions of the lower electrodes
Implementation Method 2
storage capacitors 1h including lower electrodes 3c and upper electrodes 6c, the lower electrodes 3c being portions of capacitor lines 3b, the upper electrodes 6c being extending portions of the drain regions 6b
Data Source
AI summary
An electro-optical device includes an element substrate having a plurality of pixel regions; thin-film transistors, arranged in the pixel regions, including gate electrodes, portions of a gate insulating layer, and semiconductor layers; pixel electrodes electrically connected to drain regions of the thin-film transistors; and storage capacitors including lower electrodes and upper electrodes that are opposed to the lower electrodes with insulating layers disposed therebetween, the insulating layers being made of the same material as that for forming the gate insulating layer. The upper electrodes overlap with some of end portions of the lower electrodes. The gate insulating layer has thin portions located in inner portions of regions overlapping with the lower and upper electrodes and thick portions which are located in regions overlapping with the upper electrodes and the end portions of the lower electrodes and which have a thickness greater than that of the thin portions.