Array Substrate Gray-Tone Mask Patterning

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Solution Overview

Problem

The manufacturing process of array substrates for TFT-LCDs is complex and costly due to the need for multiple patterning processes, which hinders efficiency and cost reduction.

Innovation Solution

A method utilizing a gray-tone or half-tone mask to reduce the number of patterning processes from seven to three, allowing for the efficient formation of an array substrate by sequentially coating and developing photoresist layers to define the necessary thin-film transistor components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple patterning processes (seven processes) are used to manufacture the array substrate, then the manufacturing precision and reliability are improved, but the device complexity and production cost increase

Engineering Contradiction:
Improvepatterning precisionVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines multiple patterning operations into a single integrated process. Specifically, it forms the gate electrode, active layer, source/drain electrodes, and pixel electrode patterns simultaneously in one patterning step, rather than performing separate patterning operations for each component. This merging of operations reduces the total number of patterning processes from seven to three, simplifying the manufacturing process while maintaining the required precision for each component.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent employs a gray-tone or half-tone mask that serves multiple functions simultaneously. This single mask enables the patterning of different components (gate electrode, active layer, source/drain electrodes, pixel electrode) with different pattern densities and geometries in one exposure step. The mask's ability to provide varying light transmission levels allows it to perform multiple patterning functions that would otherwise require separate masks and process steps.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If multiple patterning processes are used, then the manufacturing precision is improved, but the productivity decreases due to longer production time

Engineering Contradiction:
Improvepatterning precisionVSAvoidproduction efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent merges multiple sequential patterning operations into a single simultaneous patterning process. By forming all necessary electrode and layer patterns in one exposure and development cycle, the total process time is dramatically reduced from what would be required for seven separate patterning steps to just three integrated steps, thereby improving productivity without sacrificing pattern precision.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary structuring by forming a three-dimensional pixel electrode structure before the final patterning step. This preliminary action allows the subsequent patterning process to focus only on defining the precise patterns rather than building both structure and pattern simultaneously, enabling faster processing while maintaining high precision for the final device geometry.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If the number of patterning processes is reduced to three, then the productivity and ease of manufacture are improved, but the manufacturing precision may deteriorate

Engineering Contradiction:
Improveproduction efficiencyVSAvoidpatterning precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent replaces complex mechanical multi-step patterning operations with an optical system using gray-tone or half-tone masks. This optical approach allows multiple pattern definitions to be achieved simultaneously through light transmission variations, maintaining precision that would be difficult to achieve with reduced mechanical process steps. The optical method enables precise pattern formation through controlled light exposure rather than sequential mechanical masking.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent utilizes parameter changes in the mask's light transmission properties to achieve different pattern densities and geometries. By varying the gray-tone levels or half-tone densities in different regions of the mask, the process achieves precise control over the resulting patterns for different components. This parameter variation allows a single patterning step to produce multiple distinct patterns with different spatial frequencies and densities, maintaining precision without requiring multiple process steps.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach shortens production cycles, reduces costs, and enhances manufacturing efficiency by simplifying the process while maintaining performance standards.

Implementation Method 1

a gray-tone or half-tone mask is used as an exposure mask for exposing a photoresist layer

Methodology Applied
Scientific EffectPhotography: Photography

Implementation Method 2

exposure, development, etching, striping

Methodology Applied
Scientific EffectPhotoelectric Effect: Photoelectric Effect

Data Source

PatentEP2708943B1Array Substrate and Manufacturing Method Thereof
Publication Date: 2019.11.06 BOE TECHNOLOGY GROUP CO LTD
  • EP2708943B1 patent drawingFigure 1~3A
  • EP2708943B1 patent drawingFigure 3B~3D
  • EP2708943B1 patent drawingFigure 3E~4B

AI summary

Embodiments of the present invention relate to an array substrate and a manufacturing method thereof. The manufacturing method comprises: step 1: forming a gate line, a gate electrode (2a), a first insulating layer (3), an active layer (4) and ohmic contact layers (5) on a base substrate (1) by a first patterning process using a gray-tone or half-tone mask, in which the active layer (4) between the ohmic contact layers (5) corresponds to a channel region; step 2: forming a second insulating layer (6) and a pixel electrode film (7) on the base substrate obtained after the step 1 by a second patterning process using a gray-tone or half-tone mask; and step 3: forming a drain electrode (8b), a source electrode(8a), a data line and a passivation layer (9) on the base substrate obtained after the step 2 by a third patterning process using a gray-tone or half-tone mask.