Array Substrate Groove Design for Signal Line Short Circuit Prevention
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Solution Overview
Problem
The existing manufacturing processes for array substrates in thin film transistor liquid crystal displays (TFT-LCDs) are prone to defects such as short circuits (Data Gate Short, DGS) at the crossing regions between data and gate lines, which current methods cannot effectively prevent, leading to quality issues and increased costs.
Innovation Solution
The array substrate design incorporates a groove in the first signal line at the crossing region with the second signal line, reducing the thickness of the first signal line and increasing the distance between the lines, thereby enhancing the thickness of the insulating layer without increasing the substrate thickness, thereby reducing the risk of short circuits and improving product yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the insulating layer is increased to prevent short circuits at crossing regions, then the reliability is improved, but the substrate thickness increases
Solution Approach 1:
The patent applies local quality by creating a groove only at the crossing region where the first signal line intersects with the second signal line, rather than uniformly increasing insulating layer thickness across the entire substrate. This localized modification increases the effective insulating distance at the critical short circuit risk area while maintaining normal substrate thickness elsewhere, thus preventing short circuits without increasing overall substrate thickness.
2Reliability
If the groove depth is increased to further separate the signal lines, then the reliability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent specifies that the groove depth is controlled within a particular range (0.5-2.0 μm) to optimize the balance between reliability improvement and manufacturing feasibility. By defining this parameter range, the invention achieves sufficient line separation for short circuit prevention while keeping the groove depth within controllable limits for standard manufacturing processes, thus managing the trade-off between reliability and manufacturing precision.
Data Source
Figure 1~3A
Figure 3B~5
AI summary
The present disclosure provides an array substrate, a manufacturing method of an array substrate, and a display device. The array substrate includes: a base substrate (100); a first signal line (110), extending in a first direction and located on the base substrate (100); a second signal line (120), extending in a second direction and located on a side of the first signal line (110) away from the base substrate (100) and insulated with the first signal line (110), the first direction and the second direction crossing with each other. A side of the first signal line (110) facing the second signal line (120) is provided with a groove (111), the groove (111) is located at a crossing region between the first signal line (110) and the second signal line (120), in the crossing region, an otherographic projection of the second signal line (120) on the base substrate (100) completely falls into an orthographic projection of the groove (111) on the base substrate (100). The array substrate reduces a thickness of the first signal line at the crossing region between the first signal line and the second signal line, to increase a distance between the first signal line and the second signal line at the crossing region, so as to effectively reduce a risk of short circuit between the first signal line and the second signal line.