Array Substrate Hard Mask Layer Photomask Reduction
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Solution Overview
Problem
The manufacturing process of array substrates for full-color displays, such as active matrix liquid crystal displays and organic light-emitting diodes, is complex and costly due to the need for multiple photomasks and intricate structures, which complicates the production of high-quality thin film transistors and etching stop layers.
Innovation Solution
A simplified manufacturing method for array substrates is introduced, which adjusts the processes for semiconductor and etching stop layers, using a patterned hard mask layer to define the etching stop layer and reduce the number of photomasks required, while maintaining the quality of the thin film transistors and improving electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a complicated structure with multiple photomasks is used to improve TFT quality, then the manufacturing precision is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the formation of the etching stop layer and semiconductor layer into a single simultaneous etching process using one photomask, rather than using separate processes with multiple photomasks. This merging reduces process complexity while maintaining the protective function of the etching stop layer and the precision of TFT formation.
Solution Approach 2:
The single photomask serves multiple functions: it defines both the etching stop layer pattern and the semiconductor layer pattern simultaneously. This multi-functional approach eliminates the need for separate photomasks for each layer, reducing overall device complexity while preserving manufacturing precision.
2Manufacturing precision
If multiple photomasks are used to form etching stop layer and semiconductor layer separately, then the manufacturing precision is improved, but the productivity decreases
Solution Approach 1:
The patent merges the separate formation processes of the etching stop layer and semiconductor layer into a single simultaneous etching operation. This consolidation reduces the total number of photomasks and process steps, thereby improving productivity while maintaining pattern uniformity through precise single-mask alignment.
3Device complexity
If a simplified process with fewer photomasks is used, then the device complexity is reduced, but the manufacturing precision may deteriorate
Solution Approach 1:
The patent introduces a specifically designed photomask pattern that acts as an intermediary to simultaneously define both the etching stop layer and semiconductor layer. This intermediary pattern ensures precise line width control and pattern uniformity are maintained even though the overall process complexity is reduced.
Data Source
AI summary
The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT.