Array Substrate Insulating Intersecting Signal and Connecting Lines
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Solution Overview
Problem
Conventional array substrates face issues with electrostatic accumulation or short circuits between metal connecting lines and source-drain metal lines due to the thin passivation layer, leading to erroneous signal input and display errors.
Innovation Solution
The array substrate design includes intersecting connecting lines and signal lines with an insulating layer, where only the first electrode line layer is present in intersecting regions, and both electrode line layers are included in non-intersecting regions, ensuring reliable insulation and preventing electrostatic accumulation or short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a thin passivation layer is used between connecting lines and signal lines, then the frame width can be reduced and integration can be improved, but electrostatic accumulation and short circuits occur between the metal lines
Solution Approach 1:
The signal line is segmented into two distinct electrode line layers (first electrode line layer and second electrode line layer) in the non-intersecting region, while in the intersecting region only the first electrode line layer is present. This segmentation allows the signal line to have different structural configurations in different spatial regions, enabling reliable insulation at intersections while maintaining signal transmission functionality elsewhere.
Solution Approach 2:
The patent applies local quality by making the signal line structure region-dependent: in the first region (intersecting region), the signal line includes only the first electrode line layer to ensure insulation with connecting lines; in the second region (non-intersecting region), the signal line includes both the first and second electrode line layers to maintain proper signal transmission. This local structural variation resolves the contradiction between thin passivation and reliable insulation.
2Device complexity
If the passivation layer thickness is reduced to achieve narrow frame, then manufacturing precision requirements increase and short circuit risks increase
Solution Approach 1:
The patent transitions from a single-layer signal line structure to a multi-layer structure (first electrode line layer and second electrode line layer) in the non-intersecting region. This dimensional change in the vertical direction provides additional insulation distance and electrostatic separation between the connecting line and the signal line, reducing the reliance on thin passivation layer thickness control and thereby reducing manufacturing precision requirements.
3Reliability
If connecting lines and signal lines are designed to intersect with insulation, then signal transmission accuracy is improved, but device complexity increases due to multiple electrode line layers
Solution Approach 1:
The signal line is divided into different structural segments: in the first region (intersecting region), only the first electrode line layer is present to ensure insulation and prevent short circuits; in the second region (non-intersecting region), both the first and second electrode line layers are present to maintain proper signal transmission characteristics. This segmentation allows the device to achieve reliable signal transmission without uniformly increasing complexity across the entire structure.
Solution Approach 2:
The patent applies local quality by making the signal line structure region-dependent: in the first region (intersecting region), the signal line includes only the first electrode line layer to ensure insulation with connecting lines; in the second region (non-intersecting region), the signal line includes both the first and second electrode line layers to maintain proper signal transmission. This local structural variation resolves the contradiction between thin passivation and reliable insulation.
Data Source
AI summary
An array substrate and a display device are provided. The array substrate comprises a plurality of signal lines (40), a plurality of connecting lines (50) and a driving module (60) in a peripheral region (1) outside a display region (2); the connecting lines (50) are configured for connecting the signal lines (40) and the driving module (60), to transmit signal from the signal lines (40) to the driving module (60), wherein, at least one of the connecting lines (50) and at least one of the signal lines (40) are designed to intersect with and insulated from each other in a first region (N). The at least one of the signal lines (40) includes, in a second region (0) other than the first region (N), a first electrode line layer (401) and a second electrode line layer (402), while, in the first region (N), includes the first electrode line layer (401) but does not include the second electrode line layer (402). The array substrate may prevent problems of electrostatic accumulation or short circuit from occurring between the connecting lines (50) and the second electrode line layer (402).