Array Substrate Power Line Layout for Lower OLED IR Drop
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Solution Overview
Problem
As pixel resolutions of OLED display panels increase, metal wiring resistance increases, leading to IR drops and display unevenness due to higher resistances in signal lines, particularly power signal lines.
Innovation Solution
The array substrate design includes a first and second signal line connected through a via hole, forming a first power signal line with reduced resistance by parallel connection, and additional power signal lines connected through block electrodes and via holes, reducing IR drops and improving display uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If metal wiring is made thinner and more refined to accommodate higher pixel resolutions, then the area occupied by wiring is reduced, but the resistance of metal wires increases
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional stacked wiring structures. Multiple signal lines are arranged in different layers (first source-drain metal layer, second source-drain metal layer, gate metal layer) and connected through vertical via holes, effectively utilizing the third dimension to reduce resistance while maintaining compact area.
Solution Approach 2:
The patent combines multiple signal lines in parallel to form composite signal lines. Specifically, the first signal line and second signal line are electrically connected through via holes to form a first power signal line, and the first power signal line is further connected to the second power signal line through block electrodes, creating a merged low-resistance path.
2Reliability
If the resistance of power signal lines is reduced through parallel connections, then IR drops are minimized, but the device structure becomes more complex
Solution Approach 1:
The via holes and block electrodes serve multiple functions: they electrically connect signal lines in parallel to reduce resistance, while also forming storage capacitors when combined with gate electrodes. This multi-functionality reduces the need for separate components and mitigates structural complexity.
Solution Approach 2:
The patent implements a nested structure where the first signal line and second signal line are positioned in different layers, with via holes penetrating through insulating layers to connect them. The block electrodes are nested within the wiring structure to provide both connection and capacitance functions, creating a compact nested architecture.
Data Source
Figure 1~2
Figure 3A~3B
Figure 3C
AI summary
The disclosure discloses an array substrate, a display panel, and a display device. A first power signal line is configured to be formed by electrically connecting a first signal line located in a first source-drain metal layer and a second signal line located in a second source-drain metal layer through a via hole, which is equivalent to that the first power signal line is composed of the first signal line and the second signal line connected in parallel, and the equivalent resistance of the parallel-connected first signal line and second signal line included in the first power signal line is smaller than the resistance of any of the signal lines. Thus, the resistance of the first power signal line may be effectively reduced, so that an IR drop of a display panel with an array substrate may be reduced, and the display uniformity of the display panel is improved.