Array Substrate Layout for Wider Voltage Lines and Lower IR Drop
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display technologies face challenges in efficiently managing the layout and manufacturing of array substrates for micro LED-based displays, particularly in minimizing IR drop and optimizing the layout of voltage supply lines due to limited space, which affects the performance and cost of pixel driving circuits.
Innovation Solution
The array substrate design includes a data line, first and second voltage supply lines, and a pixel driving circuit with transistors in different layers, allowing for the separation of voltage supply lines from the data line, thereby increasing line widths to reduce IR drop and requiring additional manufacturing steps but saving costs by eliminating the need for additional mask plates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage supply lines are separated from data lines and line widths are increased to reduce IR drop, then the driving capability and performance of pixel circuits are improved, but the manufacturing process complexity increases due to additional manufacturing steps
Solution Approach 1:
The patent segments the conductive lines into two distinct types: data lines and voltage supply lines. This segmentation allows each line type to be optimized independently - voltage supply lines can have larger widths for lower IR drop, while data lines maintain their original design. The segmentation is implemented through separate patterning steps using different mask plates, resolving the contradiction between performance optimization and manufacturing simplicity.
2Manufacturing precision
If additional mask plates are used to separate voltage supply lines from data lines, then manufacturing precision and line width control are improved, but manufacturing cost increases
Solution Approach 1:
The patent divides the patterning process into separate steps for data lines and voltage supply lines, each using its own mask plate. This segmentation enables precise control of line widths for voltage supply lines to minimize IR drop, while the increased manufacturing cost is offset by the performance benefits and the elimination of the need for additional mask plates in alternative designs.
3Power
If line widths of voltage supply lines are increased to reduce IR drop, then power delivery and driving capability are improved, but the layout space consumption increases
Solution Approach 1:
The patent segments the conductive network into data lines and voltage supply lines with different width requirements. By dedicating specific regions to voltage supply lines with larger widths, the design achieves low IR drop without requiring all lines to be wide. The segmentation allows efficient space utilization where only critical power delivery paths consume additional area.
Solution Approach 2:
The patent applies local quality by assigning different line widths to different functional elements: voltage supply lines have larger widths for low resistance, while data lines maintain narrower widths for space efficiency. This localized optimization of line dimensions resolves the contradiction between power delivery capability and layout space consumption.
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
An array substrate is provided. The array substrate includes a data line; a first voltage supply line; a second voltage supply line; and a pixel driving circuit. The pixel driving circuit includes one or more transistors in a first group and one or more transistors in a second group. A source electrode and a drain electrode of at least one transistor in the first group, the data line, the first voltage supply line, and the second voltage supply line are in a same layer. A source electrode and a drain electrode of at least one transistor in the second group are in a layer different from the first voltage supply line and the second voltage supply line.