Array Substrate Leakage Current Reduction via Connection Electrode
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Solution Overview
Problem
Current manufacturing methods for array substrates, which use a halftone mask to form source, drain, and active layers, result in increased leakage current in thin film transistors, deteriorating their performance and requiring costly solutions to mitigate this issue.
Innovation Solution
The array substrate design includes a connection electrode that connects the source/drain electrode to the data line at a climbing position relative to the gate electrode, ensuring the active layer does not extend beyond the gate electrode, thereby reducing leakage current without increasing manufacturing costs by using fewer masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a halftone mask is used to form source electrode, drain electrode, and active layer together, then the number of masks is reduced and manufacturing cost is saved, but leakage current of the thin film transistor increases and performance deteriorates
Solution Approach 1:
The patent divides the electrode structure into multiple segments: a first electrode partially overlapping the gate electrode, and a second electrode positioned at a climbing position relative to the gate electrode. This segmentation allows the active layer to be confined within the gate electrode's projection area, preventing leakage current while maintaining the simplified mask process.
Solution Approach 2:
The patent introduces a vertical dimension by positioning the second electrode at a climbing position relative to the gate electrode, rather than simply extending horizontally. This dimensional change allows the electrode structure to achieve both cost-effectiveness and performance by controlling the active layer's spatial configuration in three-dimensional space.
2Ease of manufacture
If the active layer extends beyond the gate electrode, then the electrode can be formed with fewer masks, but leakage current increases and TFT performance deteriorates
Solution Approach 1:
The patent applies local quality by creating different spatial relationships between electrodes and the gate in different regions. The first electrode overlaps the gate in a controlled manner, while the second electrode is positioned at a climbing position, ensuring the active layer is precisely localized where needed without extending beyond the gate's projection area.
3Reliability
If connection electrode is added to connect first electrode to data line, then electrical connection is improved, but device complexity increases
Solution Approach 1:
The patent merges the connection electrode with existing electrode structures. The first electrode serves dual purposes: as part of the transistor structure and as a connection element to the data line. This merging approach improves electrical connection reliability without significantly increasing device complexity.
Data Source
AI summary
The present disclosure provides an array substrate, a method of manufacturing the same, and a display panel. The array substrate includes a base substrate, a thin film transistor disposed at a side of the base substrate. The thin film transistor includes a first electrode, a second electrode, and a gate electrode. The array substrate includes a data line disposed at the side of the base substrate The array substrate includes a connection electrode electrically connecting the first electrode of the thin film transistor to the data line. An orthographic projection of an active layer of the thin film transistor on the base substrate is located within an orthographic projection of the gate electrode of the thin film transistor on the base substrate.