Array Substrate Light Blocking Layer for Trace Mura Prevention
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Solution Overview
Problem
In high-resolution liquid crystal display devices using advanced-super dimensional switching mode, the small unit area of sub-pixels results in insufficient storage capacitance, leading to non-uniform photoresist thickness and pattern deformation during manufacturing, causing trace mura phenomena and image quality issues due to light blocking and light-transmitting states at common electrode lines.
Innovation Solution
An array substrate design with a light blocking layer made of conductive material positioned between common electrode lines and slit electrodes, ensuring all light is blocked at the slit tail ends, maintaining consistent photoresist thickness and pattern integrity, and enhancing storage capacitance by connecting the light blocking layer to the common electrode line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If common electrode lines are manufactured on gate layer to increase storage capacitance, then storage capacitance is improved, but photoresist thickness becomes non-uniform and patterns deform causing trace mura phenomenon
Solution Approach 1:
A light blocking layer is introduced as an intermediary between the common electrode line and the photoresist layer. This light blocking layer prevents light from reaching the photoresist at the common electrode line position during photoetching, eliminating the non-uniform photoresist thickness and pattern deformation that would otherwise occur, thus preventing trace mura phenomenon while maintaining the increased storage capacitance structure.
Solution Approach 2:
The light blocking layer is formed in advance before the photoetching process. By pre-establishing this light blocking structure at the common electrode line position, the patent prevents the subsequent photoresist thickness non-uniformity and pattern deformation issues before they can occur during the photoetching step.
2Quantity of substance
If common electrode lines are positioned nearby tail ends of slits, then storage capacitance is increased, but light blocking and light-transmitting states produce different influences on light causing photoresist thickness non-uniformity
Solution Approach 1:
The light blocking layer serves as a mediator that uniformizes the light interaction across the common electrode line region. By blocking light at the common electrode line position, it creates a consistent light blocking state that matches the surrounding areas, eliminating the differential light influence that causes photoresist thickness non-uniformity.
Solution Approach 2:
The light blocking layer is selectively positioned only at the common electrode line region where the problem occurs. This localized application of light blocking property addresses the specific issue of non-uniform photoresist thickness at the common electrode line without affecting other regions of the pixel structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution prevents pattern deviations and trace mura phenomena, maintaining image quality while improving storage capacitance by ensuring consistent photoresist thickness and enhancing capacitance formation between electrodes.
Implementation Method 1
a light blocking layer is arranged between the common electrode line and the first electrode... all light is blocked in the area of the light blocking layer
Implementation Method 2
the light blocking layer is made of a conductive material and connected to the common electrode line... enhancing storage capacitance by connecting the light blocking layer to the common electrode line
Data Source
AI summary
The present invention discloses an array substrate and a manufacturing method thereof, and a liquid crystal display device, which relate to the field of liquid crystal display technology and may keep patterns at the slit tail ends of slit electrodes consistent with predesigned patterns so as to avoid a trace mura phenomenon. The array substrate includes a plurality of sub-pixel units defined by crossing of a plurality of gate lines and a plurality of data lines, wherein a first electrode is arranged in each sub-pixel unit, the first electrode is a slit electrode, and a common electrode line is arranged below the first electrode. In each sub-pixel unit, a light blocking layer is arranged between the common electrode line and the first electrode, and both the slit tail end of the first electrode and the common electrode line are positioned in the area of the light blocking layer.