Array Substrate Multi-Tone Mask Patterning for Parasitic Capacitance Reduction
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Solution Overview
Problem
The existing manufacturing processes for liquid crystal display array substrates require multiple patterning steps, which increase costs, reduce efficiency, and can lead to parasitic capacitance due to error coverage in the overlap region between the pixel electrode and the data line.
Innovation Solution
A method involving a multi-tone mask process to form a photoresist pattern with varying thickness regions, allowing for the simultaneous etching of data lines, active layers, and pixel electrodes, reducing the number of mask processes and minimizing the formation of parasitic capacitance by using a transparent conductive thin film to connect the pixel electrode directly to the drain electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning processes with masks are used to form conductive patterns and via holes, then the manufacturing precision and reliability are improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple patterning steps into a single multi-tone mask process. The multi-tone mask contains different transparency regions (first, second, and third transparency regions) that allow simultaneous formation of pixel electrodes, data lines, and via holes in one exposure and development step, eliminating the need for separate patterning processes for each feature.
Solution Approach 2:
The multi-tone mask serves multiple functions simultaneously: it defines the pixel electrode pattern, data line pattern, and via hole positions in a single mask layer. This universal mask replaces what would traditionally require multiple specialized masks, simplifying the overall manufacturing process while maintaining precision.
2Manufacturing precision
If multiple patterning processes are used to form various patterns, then the manufacturing precision is improved, but the productivity decreases
Solution Approach 1:
The patent merges sequential patterning operations into a single parallel operation using the multi-tone mask. All critical features (pixel electrodes, data lines, via holes) are patterned simultaneously in one exposure and development cycle, dramatically reducing the total process time and improving manufacturing throughput.
Solution Approach 2:
The multi-tone mask is designed in advance with pre-calculated transparency regions that account for all subsequent patterning needs. The first, second, and third transparency regions are configured beforehand to ensure that a single exposure step produces all required patterns with correct dimensions and positions, eliminating the need for multiple sequential adjustments.
3Ease of manufacture
If conventional patterning processes are used, then the ease of manufacture is maintained, but parasitic capacitance increases due to error coverage in overlap regions
Solution Approach 1:
The multi-tone mask creates locally optimized patterns by providing different transparency levels in different regions. The first transparency region produces pixel electrodes with precise boundaries, the second transparency region forms data lines with controlled width, and the third transparency region creates via holes positioned exactly where needed. This local precision eliminates error coverage and overlapping that would otherwise generate parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs, and improves the performance of Thin-Film Transistors (TFTs) by reducing the actual line-width and minimizing parasitic capacitance, leading to enhanced display performance.
Implementation Method 1
applying a photoresist on the data line metal thin film and performing exposure and development processes by using a multi-tone mask so as to form a photoresist pattern
Implementation Method 2
forming a transparent conductive thin film on the base substrate with a remaining photoresist in the first thickness region thereon
Data Source
AI summary
An embodiment of the invention provides a method for manufacturing an array substrate, wherein the procedure for forming a data line, an active layer with a channel, a source electrode, a drain electrode and a pixel electrode comprises applying a photoresist on a data line metal thin film and performing exposure and development processes by using a multi-tone mask so as to form a photoresist pattern including a third thickness region, a second thickness region and a first thickness region whose thicknesses are successively increased, the third thickness region at least corresponding to the pixel electrode, the second thickness region corresponding to the data line, the active layer, the source electrode and the drain electrode, and the first thickness region corresponding to the other regions.