Array Substrate Layout With Parallel Metal Lines for Narrow-Bezel Displays
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Solution Overview
Problem
The complexity and cost of manufacturing ultra-narrow frame display panels are increased due to the need for additional metal layers and via holes to reduce resistance in scan and data lines, leading to signal transmission delays and increased production time.
Innovation Solution
The array substrate design incorporates a third metal layer connected in parallel with the first and second metal layers using via holes formed by a single manufacturing process, reducing the number of fabrication steps and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a third metal layer is added to reduce resistance in scan and data lines, then resistance is reduced, but manufacturing complexity and production time increase
Solution Approach 1:
The patent combines the formation of multiple via holes (first, second, and third via holes) into a single manufacturing process step. Instead of forming via holes sequentially for each metal layer connection, all necessary via holes are formed simultaneously in one etching process, reducing the total number of manufacturing steps while maintaining the parallel connection structure that reduces resistance
Solution Approach 2:
The single manufacturing process used to form via holes serves multiple functions: it creates the first via hole connecting the first and third metal layers, the second via hole connecting the second and third metal layers, and the third via hole connecting the second metal layer to the common electrode. This multi-functional approach reduces process complexity while achieving all necessary electrical connections
2Reliability
If a third metal layer is added to reduce resistance in scan and data lines, then resistance is reduced, but production cost increases
Solution Approach 1:
The patent merges multiple via hole formation steps into a single manufacturing process, reducing the total number of process steps. This consolidation reduces production time and associated costs while maintaining the resistance-reducing parallel connection structure between metal layers
3Area of stationary object
If scan lines and data lines are designed to be narrow to maintain pixel aperture ratio, then pixel aperture ratio is maintained, but resistance and capacitance increase causing signal transmission delay
Solution Approach 1:
The patent adds a third dimension (vertical stacking) to the trace structure by introducing a third metal layer with parallel scan and data lines. This vertical arrangement provides additional conduction paths without increasing the horizontal footprint, thereby maintaining pixel aperture ratio while reducing resistance and capacitance through parallel connections
Solution Approach 2:
The patent combines multiple conduction paths (original first metal layer lines and added third metal layer lines) into a parallel connection structure. This merging of conduction paths reduces the overall resistance and capacitance of the scan and data lines while keeping the narrow line width required for high pixel aperture ratio
Data Source
AI summary
An array substrate, a method for fabricating the same, and a display panel are provided. The array substrate includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer. The first metal layer includes a first data line and a first vertical scan line. The second metal layer includes a horizontal scan line. The third metal layer includes a second data line and a second vertical scan line. The second data line is connected to the first data line through a first via hole. The second vertical scan line is connected to the first vertical scan line through a second via hole. The second vertical scan line is connected to the horizontal scan line through a third via hole. The first via hole, the second via hole, and the third via hole are formed by a same manufacturing process.