Array Substrate Wire Layout for Stable Pixel Reset Voltage

The scanning line is divided into multiple wire segments (first metal wire segment, second metal wire segment, third metal wire segment, fourth metal wire segment) that extend in different directions and overlap with different semiconductor wire segments at different locations. This segmentation allows the formation of multiple reset transistors with distinct gate and anode reset functions, improving display reliability while managing wiring complexity through structured division.

The patent utilizes spatial overlap in the vertical dimension between metal wire segments and semiconductor wire segments to form transistor structures. By arranging metal wire segments to overlap with semiconductor wire segments at different positions and orientations, the patent creates multiple reset transistors without requiring additional planar space, thus improving display effect while controlling arrangement complexity.

The semiconductor wire is segmented into multiple segments (first semiconductor wire segment, second semiconductor wire segment, third semiconductor wire segment, fourth semiconductor wire segment) connected in series. Each segment forms transistors with overlapping metal wire segments at different locations. This segmentation distributes the voltage transmission function across multiple shorter segments rather than one long continuous wire, reducing the effective voltage transmission distance while maintaining transistor performance.

The patent introduces connection joints as intermediary structures between semiconductor wire segments. These connection joints serve as transition points that facilitate voltage transmission between segments while allowing the semiconductor wire to be arranged in a folded pattern. This intermediary approach enables the semiconductor wire to achieve sufficient length for forming multiple transistors while keeping each segment's voltage transmission distance manageable.