Array Substrate Protective Pattern for Via Hole Short Circuit Prevention
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Solution Overview
Problem
In the manufacturing of array substrate assemblies for liquid crystal display panels, the conventional process of forming via holes can lead to short circuits between the gate line and the common electrode signal line due to the close proximity and small diameter of these features, making it difficult to accurately create connections without cutting through the gate insulating layer and causing abnormalities in the substrate.
Innovation Solution
The introduction of a protective pattern, which can be disposed in various layers such as the active layer, source-drain electrode layer, or on the passivation layer, helps to ensure that only the common electrode signal line is exposed during the formation of via holes by aligning the orthogonal projections of the protective pattern and via hole, preventing the gate line from being connected and thus avoiding short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the passivation layer and gate insulating layer are cut through in one etching step to form the via hole, then production efficiency is improved, but the risk of short circuit between gate line and common electrode signal line increases
Solution Approach 1:
The patent introduces a protective pattern formed in advance over the gate line before the via hole etching process. This protective pattern acts as a preliminary protective measure that prevents the gate insulating layer from being completely removed during the etching process, thereby avoiding short circuits while maintaining the efficiency of single-step etching
Solution Approach 2:
The protective pattern serves as an intermediary layer between the etching process and the gate line. It mediates the etching process by being selectively removed only where the via hole needs to be formed, while protecting adjacent areas to prevent unwanted etching and short circuits
2Reliability
If the diameter of the via hole is increased to ensure proper connection, then connection reliability is improved, but the likelihood of cutting through the gate insulating layer and causing short circuit increases
Solution Approach 1:
The protective pattern is applied locally and selectively - it is present only in specific regions where protection is needed, with openings precisely positioned where via holes should be formed. This allows large via holes to be formed with proper connection reliability while preventing short circuits through localized protection
Data Source
AI summary
A method of manufacturing an array substrate assembly and an array substrate assembly manufactured by the method are disclosed. The method includes: manufacturing a gate metal layer on a substrate, the gate metal layer including a gate line and a common electrode signal line spaced from each other; forming a gate insulating layer, an active layer, a source-drain electrode layer, a passivation layer, and a protective pattern on the gate metal layer; and forming, in the passivation layer and the gate insulating layer, a via hole configured for a connection to the common electrode signal line. An orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the via hole on the substrate partly coincide with each other, and the orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the gate line on the substrate partly coincide with each other.