Array Substrate Signal Line Protection via Gate Insulating Via Hole
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Solution Overview
Problem
The existing array substrate manufacturing process faces issues with high metal loss in signal lines due to process fluctuations and corrosion from water vapor, leading to unreliable signal transmission performance, primarily because the signal line is exposed and made of Indium tin oxide (ITO) with low compactness.
Innovation Solution
The array substrate design includes a gate insulating layer with a via hole overlapping the signal line, allowing the source-drain electrode wire to connect directly to the signal line with reduced via hole depth, and using materials like aluminum, tantalum, or molybdenum for the metal patterns and silicon dioxide or silicon nitride for passivation, which enhances compactness and protects the signal line from corrosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the signal line is made of ITO and left exposed, then the manufacturing process is simple, but the signal line suffers from metal loss and corrosion leading to unreliable signal transmission
Solution Approach 1:
The patent applies composite materials by combining ITO signal line with a protective passivation layer (silicon nitride or silicon dioxide) and source-drain electrode metal layer. This composite structure maintains the electrical conductivity of ITO while adding corrosion resistance and mechanical protection, resolving the contradiction between manufacturing simplicity and signal transmission reliability.
Solution Approach 2:
The patent creates an inert environment by forming a passivation layer (silicon nitride or silicon dioxide) over the signal line and electrode wires. This passivation layer acts as a barrier against water vapor and oxygen, preventing corrosion of the metal components and ensuring long-term reliability without complicating the manufacturing process.
2Reliability
If the via hole depth is reduced for direct connection, then the electrode wire breakage risk decreases, but the connection structure becomes more complex
Solution Approach 1:
The patent applies preliminary action by pre-forming the gate insulating layer with via holes before forming the source-drain electrode metal layer. This sequence allows the electrode wires to be directly connected to the signal line through pre-prepared pathways, reducing via hole depth requirements and minimizing breakage risk while maintaining structural simplicity.
Solution Approach 2:
The patent merges the gate insulating layer formation with the via hole creation process. The gate insulating layer is formed with integrated via holes that serve dual purposes: electrical connection pathways and structural support. This merging reduces the need for separate deep via hole formation steps, simplifying the overall connection structure while improving reliability.
Data Source
AI summary
There is provided an array substrate, a manufacturing method therefor, a display panel, and a display device. The array substrate includes: a base substrate, and a gate metal pattern, a gate insulating layer and a source-drain metal pattern which are sequentially disposed on the base substrate. The gate metal pattern includes a signal line and a gate electrode, the signal line is in the peripheral area, the gate insulating layer is provided with a first via hole penetrating the gate insulating layer, the orthogonal projection of the first via hole on the base substrate and the orthogonal projection of the signal line on the base substrate have an overlapping area, the source-drain metal pattern includes a source-drain electrode wire, and the source-drain electrode wire is electrically connected to the signal line through the first via hole. The present disclosure achieves the function of protecting the signal line.