Array Substrate Single Patterning Process for Display Devices
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Solution Overview
Problem
The existing method of manufacturing array substrates for multi-dimensional electric field display panels is complex, resulting in low production efficiency and high costs due to the need for multiple patterning processes.
Innovation Solution
A method that simplifies the manufacturing process by completing the formation of key components such as active layers, sources, drains, data lines, and pixel electrodes in a single patterning process, along with forming gate and gate lines in another single process, using dual-tone masks and plasma processing to reduce complexity and material consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning processes are used to form different components (common electrode, gate, source, drain, pixel electrode), then manufacturing precision and component quality are maintained, but device complexity and manufacturing time increase significantly
Solution Approach 1:
The patent combines multiple patterning processes into a single patterning step by forming the common electrode, gate electrode, source electrode, drain electrode, and pixel electrode simultaneously using one photoresist layer and one etching process. This merging approach reduces process complexity while maintaining manufacturing precision through careful control of the single patterning step.
Solution Approach 2:
The single patterning process serves multiple functions: it defines patterns for the common electrode, gate electrode, source electrode, drain electrode, and pixel electrode all in one step. This multi-functional approach eliminates the need for separate patterning processes for each component, thereby reducing overall device complexity.
2Reliability
If six or seven patterning processes are used to form all components, then complete component formation is achieved, but productivity decreases and manufacturing cost increases
Solution Approach 1:
The patent merges six or seven separate patterning processes into a single patterning process that forms all electrode components simultaneously. This dramatic reduction in the number of steps directly increases productivity and production efficiency while maintaining complete component formation through the comprehensive design of the single patterning step.
Solution Approach 2:
The patent performs preliminary planning in the process design stage to enable all components to be formed in one patterning step. By carefully designing the photoresist coating, exposure, and etching parameters in advance, the single patterning process can reliably form all required components without needing multiple subsequent patterning steps.
3Manufacturing precision
If multiple patterning processes are used, then all components are formed with proper patterns, but manufacturing cost and time consumption increase
Solution Approach 1:
The patent combines multiple patterning operations into one simultaneous patterning process, reducing the total manufacturing cycle time while maintaining pattern accuracy through optimized single-step patterning parameters. This eliminates the sequential time consumption of multiple separate patterning steps.
Solution Approach 2:
The single patterning process performs continuous useful action by forming all electrode patterns in one uninterrupted etching step, rather than stopping and starting multiple times across six or seven separate processes. This continuous operation reduces total manufacturing time while maintaining consistent pattern quality throughout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases production efficiency, reduces manufacturing costs, and enhances economic benefits by minimizing the number of patterning steps and material usage, while maintaining the quality of the array substrate components.
Implementation Method 1
coating a photoresist on the semiconductor film, exposing the photoresist with a dual tone mask and developing to completely remain the photoresist corresponding to an active layer region, to partially remain the photoresist corresponding to regions of the source, the drain, the data line and the pixel electrode, and to completely remove the photoresist in remaining regions so as to expose the semiconductor film
Implementation Method 2
transforming the exposed semiconductor film into conductor by plasma processing to form the pattern comprising the active layer, the source, the drain, the data line and the pixel electrode
Implementation Method 3
ashing the photoresist to thin the photoresist corresponding to the active layer region and to expose the semiconductor film in regions other than the active layer region
Data Source
AI summary
Disclosed is an array substrate and a display device. The array substrate includes: a plurality of gate lines and a plurality of data lines formed on a base substrate, and a plurality of pixel units defined by the plurality of gate lines and the plurality of data lines intersecting each other, wherein each pixel unit includes a thin film transistor and a pixel electrode connected with the thin film transistor, the pixel electrode, the data line, as well as an active layer, a source and a drain of the thin film transistor are disposed in a same layer and are formed through a single patterning process.