Array Substrate Storage Capacitor Segmentation for OLED

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Solution Overview

Problem

The existing array substrates for organic electroluminescent display devices with polycrystalline silicon thin film transistors require numerous mask processes, which are time-consuming and costly, and face challenges in increasing storage capacitor capacitance without decreasing the aperture ratio.

Innovation Solution

A method of fabricating an array substrate with a reduced number of mask processes by forming multiple storage capacitors in parallel and optimizing the layout of electrodes and insulating layers, including a semiconductor layer, gate insulating layers, and storage electrodes, to enhance capacitance while minimizing manufacturing steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the area of electrodes of the storage capacitor is increased to increase capacitance, then the capacitance of the storage capacitor is improved, but the aperture ratio of the display device is decreased

Engineering Contradiction:
Improvestorage capacitor capacitanceVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The storage capacitor is divided into multiple capacitors connected in parallel. Specifically, the storage electrode is segmented into multiple regions (first storage electrode region, second storage electrode region, third storage electrode region) that are electrically connected in parallel, allowing increased total capacitance without requiring a single large electrode area, thus preserving aperture ratio.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the number of mask processes is reduced from nine to seven, then the manufacturing time and costs are decreased, but the manufacturing precision and reliability may be affected

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidfabrication accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

Multiple mask processes are merged into fewer steps. The patent combines the formation of multiple insulating layers (first gate insulating layer, second gate insulating layer, inter insulating layer, passivation layer) and electrode patterns into a reduced sequence of seven mask processes, maintaining precision while improving efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Insulating layers are formed in advance before electrode patterning. The first gate insulating layer, second gate insulating layer, and inter insulating layer are deposited beforehand to establish proper insulation structures, allowing subsequent electrode formation steps to proceed with fewer mask processes while maintaining manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution reduces the number of mask processes from nine to seven, decreases manufacturing time and costs, and increases storage capacitance per unit area by connecting storage capacitors in parallel, thereby improving the efficiency and performance of the organic electroluminescent display device.

Implementation Method 1

forming ohmic contact layers by doping impurities into both sides of the semiconductor layer using the gate electrode as a doping mask

Methodology Applied
Scientific EffectDoping: Dopants

Data Source

PatentUS8883579B2Array substrate for organic electroluminescent display device and method of fabricating the same
Publication Date: 2014.11.11 LG DISPLAY CO LTD
  • US8883579B2 patent drawing
  • US8883579B2 patent drawing
  • US8883579B2 patent drawing

AI summary

A method of fabricating an array substrate for an organic electroluminescent display device includes forming a semiconductor layer, a semiconductor dummy pattern, a first storage electrode and a first gate insulating layer on a substrate; forming a second gate insulating layer on the semiconductor layer and the first storage electrode; forming a gate electrode and a second storage electrode on the second gate insulating layer; forming ohmic contact layers by doping impurities into both sides of the semiconductor layer; forming an inter insulating layer on the gate electrode and the second storage electrode; forming source and drain electrodes and a third storage electrode on the inter insulating layer; forming a passivation layer on the source and drain electrodes and the third storage electrode; forming a first electrode and a fourth storage electrode on the passivation layer; and forming a spacer and a bank on the first electrode.