Integrated Test Unit for Array Substrate Testing
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Solution Overview
Problem
Current display manufacturing processes face inefficiencies due to the dispersed distribution of multiple test elements in non-display regions, which occupy significant space, increase testing costs, and reduce test efficiency, especially for high-resolution polysilicon displays where defects can lead to substantial waste if not detected promptly.
Innovation Solution
An array substrate design with integrated test units in non-display regions, featuring test block and line patterns in different layers, connected to test transistors, allowing for simultaneous optical and electrical testing without the need for frequent equipment movement, thereby reducing space and cost while enhancing testing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple test elements are disposed independently in different layers of the non-display region, then the testing coverage is comprehensive, but the space occupied in the non-display region is large
Solution Approach 1:
The patent combines multiple independent test elements (test block pattern and test line pattern) into a single integrated test unit. The test block pattern and test line pattern are formed in different layers but integrated within the same test unit structure, allowing comprehensive testing of pattern sizes and overlapping between layers while occupying reduced space in the non-display region.
2Adaptability or versatility
If multiple independent test elements are distributed in the non-display region, then all process parameters can be tested, but the testing equipment needs to be moved frequently
Solution Approach 1:
The patent integrates multiple test functions into a single test unit that can be tested by one piece of testing equipment. The test block pattern and test line pattern are positioned such that a single optical testing equipment can simultaneously or sequentially test both patterns without requiring frequent movement, thereby improving test efficiency while maintaining comprehensive process parameter testing capability.
3Reliability
If test elements are dispersedly distributed in the non-display region, then the testing function is complete, but the manufacturing cost increases
Solution Approach 1:
The patent merges multiple test elements into a compact integrated test unit with reduced overall area. The test block pattern and test line pattern are integrated within the same test unit structure, reducing the total space required in the non-display region and thereby reducing manufacturing costs while maintaining complete testing functionality.
4Measurement precision
If multiple independent test elements are used, then the testing accuracy is sufficient, but the time effectiveness of testing is reduced
Solution Approach 1:
The patent integrates multiple test patterns into a single test unit that can be tested simultaneously or in rapid succession by a single piece of equipment. The test block pattern and test line pattern are positioned to allow efficient testing without frequent equipment movement, thereby reducing testing time while maintaining sufficient testing accuracy through the integrated multi-layer pattern design.
Data Source
AI summary
An array substrate includes multiple pattern layers disposed in a display region and a test unit disposed in a non-display region, the test unit includes at least one of a test component and a test transistor. The test component includes a test block pattern and a test line pattern; the test block pattern is disposed in the same layer as one layer of the multiple pattern layers, the test line pattern is disposed in the same layer as one layer of the multiple pattern layers, and the test block pattern and the test line pattern are disposed in different layers; the orthographic projection of the test line pattern on the array substrate surrounds the periphery of the orthographic projection of the test block pattern on the array substrate; and the test block pattern or the test line pattern is connected to the test transistor.