Array Substrate Via Hole Contact for LCD Delamination

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Solution Overview

Problem

Conventional TFT-LCD array substrates using advanced-super dimensional switching technology face issues with delamination and poor contact between transparent common electrodes and gate metal common electrodes due to crystallization of amorphous indium tin oxide, leading to ineffective signal transfer and display quality problems.

Innovation Solution

The solution involves forming via holes in the insulation layer that contact both the gate metal common electrodes and the first layer transparent common electrode, allowing the second layer transparent common electrode to connect electrically with both, ensuring proper signal transfer even if delamination occurs, thereby maintaining pixel operation and display quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If amorphous indium tin oxide thin film is used to form the first layer transparent common electrode and subjected to high temperature deposition (above 300°C), then the gate insulation layer can be properly formed, but the a-ITO undergoes crystallization reaction converting to p-ITO which causes strip and delamination between the first layer transparent common electrode and the gate metal common electrode

Engineering Contradiction:
Improvedeposition temperatureVSAvoidcontact stability
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent introduces a second layer transparent common electrode separated from the first layer transparent common electrode by an insulation layer with via holes. This segmentation prevents the direct contact and potential delamination between the a-ITO layer and gate metal common electrode, while still maintaining electrical connectivity through the via holes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a gate metal common electrode as an intermediary layer between the first layer transparent common electrode and the second layer transparent common electrode. This intermediary structure allows the a-ITO to be deposited at high temperatures without directly contacting the gate metal, preventing delamination while maintaining electrical connectivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the first layer transparent common electrode and gate metal common electrode are in direct contact, then electrical connection is achieved, but delamination occurs during crystallization causing poor contact and ineffective signal transfer

Engineering Contradiction:
Improvesignal transfer efficiencyVSAvoidadhesion strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent segments the electrical connection path into multiple routes: direct contact through via holes, and indirect contact through the gate metal common electrode. This segmentation ensures that even if one path fails due to delamination, other paths maintain signal transfer efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the structural parameters of the electrode system by introducing a second layer transparent common electrode and modifying the via hole configuration. This parameter change transforms the single direct contact interface into multiple contact interfaces, improving both adhesion strength and signal transfer reliability.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If via holes are formed to connect the second layer transparent common electrode with both the gate metal common electrode and the first layer transparent common electrode, then electrical connectivity is maintained even with delamination, but the manufacturing process complexity increases

Engineering Contradiction:
Improvecontact reliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The via holes serve multiple functions: they provide electrical connection between the second layer transparent common electrode and the first layer transparent common electrode, and also maintain connection with the gate metal common electrode. This multi-functionality reduces the need for additional separate connection structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements a nested structure where the via holes are formed within the insulation layer and extend to contact multiple electrode layers. The second layer transparent common electrode is nested above the insulation layer, which is nested above the first layer transparent common electrode, creating a compact multi-layer configuration.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration ensures effective voltage signal transfer across adjacent pixel rows, preventing abnormal pixel operation and enhancing display quality by maintaining contact between electrodes despite potential delamination.

Implementation Method 1

the a-ITO thin film will undergo a crystallization reaction under such a high temperature and be converted into polycrystalline indium tin oxide (p-ITO) thin film

Methodology Applied
Scientific EffectCrystallization: Crystallisation

Data Source

PatentEP2518558B1Liquid crystal display and array substrate
Publication Date: 2016.08.24 BOE TECHNOLOGY GROUP CO LTD
  • EP2518558B1 patent drawingFigure 1~2
  • EP2518558B1 patent drawingFigure 3~4
  • EP2518558B1 patent drawingFigure 5~6

AI summary

Embodiments of the disclosed technology disclose an array substrate and a liquid crystal display. The array substrate comprises: a base substrate; a first layer transparent common electrode formed on the base substrate; a gate metal common electrode formed on the first layer transparent common electrode; an insulation layer formed on the gate metal common electrode, with via holes being formed in the insulation layer; and a second layer transparent common electrode formed on the insulation layer. A side portion of via holes is in contact with the gate metal common electrode, another side portion is in contact with the first layer transparent common electrode, such that the second layer transparent common electrode is connected electrically with the first layer transparent common electrode and the gate metal common electrode in the via holes.