Array Substrate Motherboard via-hole Depth Control
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Solution Overview
Problem
The formation of film layer patterns for different display products on a shared array substrate often results in Mura due to uneven diffusion of alignment films at deep holes with varying densities, leading to display defects.
Innovation Solution
A method involving the reduction of insulation layer thickness at regions with higher deep hole densities, allowing for via-holes to penetrate through multiple insulation layers, and forming conductive patterns connected through these via-holes, using photoresist and etching processes with grey-tone or half-tone mask plates to control the thickness and pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If film layer patterns for different display products are formed on the same array substrate, then substrate utilization is improved and manufacture cost is reduced, but Mura occurs due to uneven alignment film diffusion at deep holes with varying densities
Solution Approach 1:
The patent applies local quality by making the insulation layer thickness non-uniform across different regions of the array substrate. Specifically, the insulation layer thickness is adjusted according to the deep hole density of each display product region, creating locally optimized conditions that prevent Mura while maintaining high substrate utilization for multiple display products
Solution Approach 2:
The patent changes the physical parameter of insulation layer thickness to resolve the contradiction. By reducing the insulation layer thickness at regions with high deep hole density and maintaining normal thickness at regions with low deep hole density, the alignment film diffusion is optimized locally, preventing Mura while allowing multiple display products to share the same substrate
2Manufacturing precision
If the insulation layer thickness is reduced at the first region to decrease via-hole depth, then alignment film diffusion is improved and Mura is prevented, but additional manufacturing steps are required
Solution Approach 1:
The patent applies preliminary action by adjusting the insulation layer thickness before forming the via-holes and conductive patterns. The insulation layer is selectively thinned at the first region prior to via-hole formation, which simplifies subsequent processing and ensures proper alignment film diffusion without adding complex post-processing steps
Solution Approach 2:
The patent merges multiple functions into the insulation layer structure. The insulation layer simultaneously serves as an electrical insulator, a mechanical support, and a diffusion control element for the alignment film. By integrating the diffusion control function into the existing insulation layer through selective thickness adjustment, the patent avoids adding separate complex control mechanisms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents Mura by reducing the depth of via-holes and improving alignment film diffusion, enhancing the display quality by maintaining the conventional manufacturing process while reducing production costs and increasing efficiency.
Implementation Method 1
applying a positive photoresist onto the insulation layer, exposing the positive photoresist using a grey-tone mask plate including a fully-transparent pattern corresponding to a region where the via-hole structure is to be formed, a partially-transparent pattern corresponding to the first region other than the region where the via-hole structure is to be formed, and a nontransparent region corresponding to the second region other than the region where the via-hole structure is to be formed; developing the positive photoresist to form a photoresist partially-reserved region, a photoresist unreserved region and a photoresist fully-reserved region
Implementation Method 2
etching off the insulation layer at the photoresist unreserved region, so as to form the via-hole structure penetrating through the insulation layer; and removing the positive photoresist at the photoresist partially-reserved region, and etching the insulation layer at the photoresist partially-reserved region, so as to reduce the thickness of the insulation layer at the photoresist partially-reserved region
Data Source
AI summary
An array substrate motherboard, a manufacturing method thereof and a display device are provided. The manufacturing method includes forming a film layer pattern for a first display product at a first region of a base substrate and forming a film layer pattern for a second display product at a second region of the base substrate. The first display product has deep holes at a density larger than the second display product, and each deep hole is a via-hole penetrating through at least two insulation layers. Specifically, the manufacturing method include: prior to forming a second conductive pattern on an insulation layer, reducing a thickness of the insulation layer at the first region; and forming the second conductive pattern on the insulation layer, and enabling the second conductive pattern to be connected to a first conductive pattern under the insulation layer through a via-hole structure penetrating through the insulation layer.