Array Substrate Via Hole Depth Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing manufacturing methods for thin film transistor array substrates result in deep via holes, leading to uneven diffusion of the alignment layer and poor image quality due to rough surfaces, causing issues like black Mura and white spots in display panels.
Innovation Solution
The array substrate design includes a source/drain metal filling part within the via holes, reducing the depth of the holes and improving the smoothness of the substrate, achieved through a method involving one-time patterning processes for forming common electrode lines, gate insulating layers, and transparent connection parts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via holes are formed to connect common electrode lines on the same layer, then electrical connection is achieved, but the via holes become deep causing rough surfaces and uneven alignment layer diffusion
Solution Approach 1:
The patent introduces a multi-layer structure where common electrode lines are connected through different vertical levels. Instead of forming deep via holes through a single layer, the connection is achieved by routing lines through multiple layers (first common electrode line layer, second common electrode line layer) with via holes formed only through the passivation layer, not through deep insulating layers.
Solution Approach 2:
The patent segments the common electrode line connection into multiple parts: first common electrode lines on a gate metal layer, second common electrode lines on a source/drain metal layer, and connection via holes forming vertical interconnections. This segmentation allows each via hole to be shallower while achieving the same electrical connection function.
2Reliability
If deep via holes are formed in the passivation layer, then common electrode lines are connected, but the rough surface causes black Mura and white spots defects
Solution Approach 1:
The patent uses a multi-layer approach where common electrode lines are distributed across different vertical levels. The via holes only need to penetrate the passivation layer rather than forming deep holes through multiple insulating layers, thereby creating a smoother surface that reduces optical defects like black Mura and white spots.
Solution Approach 2:
The patent applies different structural qualities to different regions: the first common electrode lines are formed on the gate metal layer with associated via holes, while second common electrode lines are formed on the source/drain metal layer. This local differentiation allows optimization of each region's connection depth and surface quality.
Data Source
AI summary
The present invention provides an array substrate, its manufacturing method, and a display device. The array substrate comprises a gate metal layer, a gate insulating layer, a source/drain metal layer, first common electrode lines arranged on an identical layer to the gate metal layer, a first via hole arranged in the gate insulating layer and corresponding to the first common electrode line, a source/drain metal filling part arranged within the first via hole, a second via hole in communication with the first via hole, and a transparent connection part. The first common electrode lines are, by means of the transparent connection part and the source/drain metal filling part, in electrical connection with each other through the second via hole. According to the present invention, it is able to reduce the depth of the via holes in the array substrate, and improve the uneven diffusion of an alignment layer.