Array Substrate Via Opening and Conductive Layer Formation

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Solution Overview

Problem

The existing methods for manufacturing array substrates often result in nonconducting complexes forming during the anneal process, which blocks signal transmission and affects the electrical performance of the substrate due to the reaction between photoresist materials and metal components.

Innovation Solution

A modified manufacturing method where a conductive connection layer is formed to cover the via walls, preventing exposure and reaction between the flat layer and the source/drain, and employing a single mask for via opening to reduce production costs and time, using Silicon Oxide or Silicon Nitride passivation layers with specific thickness and via sizes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the flat layer is annealed to improve its properties, then the flat layer's performance is improved, but the photoresist material reacts with the metal material of the source/drain to form nonconducting complexes that block signal transmission

Engineering Contradiction:
Improveelectrical propertyVSAvoidnonconducting complex formation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a first transparent conductive layer as an intermediary between the flat layer and the source/drain metal. This intermediate layer prevents direct contact and chemical reaction between the photoresist material in the flat layer and the metal material, while still allowing electrical connection through the conductive path. The intermediary layer thus enables the anneal process to proceed without generating harmful nonconducting complexes.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If multiple masks are used to prevent contact between flat layer and source/drain, then the nonconducting complex formation is prevented, but the process time increases and production cost increases

Engineering Contradiction:
Improveelectrical propertyVSAvoidprocess time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the function of multiple masks into a single first transparent conductive layer. Instead of using separate masks to prevent contact between the flat layer and source/drain, the conductive layer is deposited to simultaneously serve as both the electrical connection path and the protective barrier. This consolidation reduces the number of process steps and masks required, thereby decreasing process time and production cost while maintaining electrical reliability.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If multiple masks are used to protect against nonconducting complex formation, then the electrical property is improved, but the manufacturing complexity increases

Engineering Contradiction:
Improveelectrical propertyVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple protective functions into a single first transparent conductive layer that serves as both the common electrode and the protective barrier against nonconducting complex formation. This reduces manufacturing complexity by eliminating the need for multiple separate masks and their associated alignment and processing steps, while still ensuring reliable electrical properties.

Inventive Principle:
Principle #5Merging (Combining)

4Reliability

If the conductive connection layer covers the via walls to prevent reaction, then the nonconducting complex formation is prevented, but the amount of material used increases

Engineering Contradiction:
Improveelectrical propertyVSAvoidmaterial amount
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The conductive connection layer is applied locally to cover only the via walls where the risk of nonconducting complex formation occurs, rather than uniformly across the entire substrate. This localized application prevents material waste while still providing effective protection at the critical interfaces between the flat layer and source/drain structures.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method ensures smooth signal transmission and enhances the electrical properties of the array substrate by preventing the formation of nonconducting complexes, reducing production costs, and improving the substrate's performance.

Implementation Method 1

a conductive connection layer separately located with the common electrode, and the conductive connection layer covers via walls of the first via and the second via

Methodology Applied
Scientific EffectPhysical barrier protection:

Implementation Method 2

as implementing anneal process to the flat layer 500, the photoresist material of the flat layer 500 in the first via 410 will react with the metal material of the source/the drain 30

Methodology Applied
Scientific EffectThermal annealing: Annealing

Implementation Method 3

the photoresist material of the flat layer 500 in the first via 410 will react with the metal material of the source/the drain 30, and generate the nonconducting complex 550

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Implementation Method 4

the pixel electrode contacts with the source/the drain 30 through the third via 710... achieve conduction of the pixel electrode and the source/the drain

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS10103173B2Manufacture method of array substrate and array substrate manufactured by the method
Publication Date: 2018.10.16 TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD
  • US10103173B2 patent drawing
  • US10103173B2 patent drawing
  • US10103173B2 patent drawing

AI summary

The present invention provides a manufacture method of an array substrate and an array substrate manufactured by the method. By employing one mask to achieve the via opening process to the flat layer and the first passivation layer, one mask can be saved to decrease the production cost and to reduce the process time; the conductive connection layer covering the first via on the flat layer and the second via on the first passivation layer are formed at the same time while forming the common electrode, and thus to prevent that the source/the drain and the flat layer to be exposed in the environment for eliminating the possibility that the two generate the reaction, which is beneficial for raising the electrical property of the array substrate and realizing the signal conduction. In the array substrate, the signal transmission is smooth, and the substrate possesses the great electrical property.