Array Substrate Insulating-Layer Etching for Undercut-Free Via Holes

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Solution Overview

Problem

Existing array substrates face issues with undercut structures or over-etching of line-changing holes and via holes due to different etching rates of insulating materials, leading to poor contact impedance and potential line breakage.

Innovation Solution

The array substrate is designed with a layered structure of insulating materials where the first type of via holes penetrate through three layers with a greater depth and diameter than the second type, allowing for initial etching of the first type and simultaneous etching of both, eliminating undercut structures and reducing over-etching, while increasing contact areas and reducing impedance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If deep line-changing holes and shallow line-changing holes are etched simultaneously to reduce the etching process, then the manufacturing process is simplified, but undercut structures or over-etching of the line-changing holes occur due to different etching rates of different insulating materials

Engineering Contradiction:
Improveetching process efficiencyVSAvoidvia hole dimensional accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent segments the via holes into two types: first type of via holes (deep, penetrating through first, second, and third insulating layers) and second type of via holes (shallow, penetrating through third insulating layer only). This segmentation allows different etching control strategies to be applied to each type, resolving the contradiction between process efficiency and dimensional accuracy by enabling selective etching approaches for different depth requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by creating regions with different via hole configurations: the first region contains first type of via holes with greater depth and diameter, while the second region contains second type of via holes with lesser depth and diameter. This local differentiation allows the etching process to be optimized for each region's specific requirements, preventing undercut structures in deep via holes while avoiding over-etching in shallow via holes.

Inventive Principle:
Principle #3Local quality

2Reliability

If multiple layers of insulating materials are used to insulate metal materials of different layers, then electrical insulation is improved, but the complexity of forming line-changing holes increases due to the need to etch through multiple layers

Engineering Contradiction:
Improveelectrical insulationVSAvoidvia hole formation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the insulating layers into three distinct layers (first, second, and third insulating layers) with different etching rates, where the second insulating layer has a lower horizontal etching rate than the first and third layers. This segmentation enables selective etching behavior that simplifies the overall formation process while maintaining the necessary electrical insulation between metal layers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent utilizes parameter changes by selecting insulating materials with different horizontal etching rates for each layer. The second insulating layer is specifically chosen to have a lower horizontal etching rate compared to the first and third layers, which enables the etching process to naturally stop or slow down at appropriate depths, reducing the complexity of forming precise line-changing holes through multiple layers.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240128271A1Array substrate, method for manufacturing array substrate, and display panel
Publication Date: 2024.04.18 GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
  • US20240128271A1 patent drawing
  • US20240128271A1 patent drawing
  • US20240128271A1 patent drawing

AI summary

Provided is a array substrate, a manufacturing method thereof, and a display panel. The array substrate comprises a laminated substrate, a first insulating layer, a second insulating layer, and a third insulating layer, wherein a horizontal etching rate of the second insulating layer is less than that of the first insulating layer and the third insulating layer. The array substrate comprises a first region provided with a first type of via holes and a second region provided with a second type of via holes, the first type of via holes penetrates through the first, second and third insulating layers, and the second type of via holes penetrates through the third insulating layer. In the present disclosure, undercut structures formed in the first type of via holes can be eliminated through two etching processes, thus avoiding over-etching of the second type of via holes.