Phase-Shifted ASIC Clocking to Reduce Switching Noise
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Solution Overview
Problem
Synchronous digital logic devices experience issues with resonant circuit noise and increased power consumption due to large numbers of transistors toggling simultaneously, which are exacerbated by high clock frequencies, and require inefficient rebuffering to correct timing errors.
Innovation Solution
Implement phase-shifted-clock domains within a single clock domain to stagger the state change times of transistors, using delay-locked loops to generate phase-shifted-clocks from a common reference clock, and employ asynchronous data transfer with FIFO buffers to manage clock domain crossings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If synchronous circuits use a single global clock to synchronize multiple blocks, then clock drift problems are avoided, but resonant circuit noise and power consumption increase due to large numbers of transistors toggling simultaneously
Solution Approach 1:
The patent divides the single clock domain into multiple phase-shifted-clock domains, where each domain uses a clock signal with a different phase offset. This segmentation allows transistor toggling to be distributed across different time phases, reducing simultaneous switching activity and thereby decreasing resonant circuit noise while maintaining overall system synchronization through the phase-shifted relationship between domains.
2Productivity
If clock frequency is increased to improve processing speed, then productivity increases, but resonant circuit noise and power consumption are amplified
Solution Approach 1:
The patent employs periodic phase-shifting of clock signals across different domains, where each domain operates at the same high frequency but with staggered phase offsets. This periodic distribution of clock edges ensures that transistor toggling occurs in a more evenly distributed manner over time, reducing peak noise levels while maintaining the high processing speed enabled by the elevated clock frequency.
3Object-generated harmful factors
If multiple independent local clocks are used for different blocks, then resonant circuit noise is reduced, but clock drift requires inefficient rebuffering operations
Solution Approach 1:
The patent introduces phase-shifted-clock domains as an intermediary solution between independent local clocks and a single global clock. Each phase-shifted-clock domain maintains its own clock signal (reducing noise) but all domains are derived from and synchronized to the same reference clock through controlled phase shifts (eliminating drift). This intermediary structure allows direct communication between domains without requiring rebuffering operations, as the phase-shifted relationship provides a predictable timing framework for data transfer.
4Ease of operation
If a single global clock is used to synchronize blocks, then data transfer between blocks is simplified, but power consumption increases due to simultaneous transistor toggling
Solution Approach 1:
The patent segments the clock distribution into multiple phase-shifted domains, where each domain handles specific data transfer operations. This segmentation distributes the transistor toggling activity across different time phases, reducing peak power consumption while maintaining simplified data transfer protocols within each domain. The phase-shifted relationship between domains provides a structured framework for inter-domain communication without requiring complex synchronization mechanisms.
Data Source
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AI summary
An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.