Phase-Shifted ASIC Clock Domains for Resonant Noise Reduction
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Solution Overview
Problem
Synchronous digital logic devices face issues with clock drift and resonant circuit noise due to synchronized transistor state transitions, leading to increased power consumption and complexity, especially in modern devices with high transistor density.
Innovation Solution
Divide clock domains into phase-shifted-clock domains, where each domain operates at the same frequency but with a phase shift relative to a common reference clock, reducing transistor resonance and power consumption by staggering state transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous circuits use the same global clock for multiple blocks, then clock drift problems are avoided, but resonant circuit noise increases due to large numbers of transistors toggling at once
Solution Approach 1:
The patent divides the clock domain into multiple phase-shifted-clock domains, where each domain uses the same clock frequency but with different phase shifts. This segments the simultaneous transistor toggling into staggered groups, reducing resonant circuit noise while maintaining clock synchronization across the entire system.
2Speed
If clock frequency is increased to improve performance, then processing speed increases, but resonant circuit noise and power consumption are amplified
Solution Approach 1:
By segmenting the clock domain into phase-shifted sub-domains, the patent enables higher clock frequencies to be used without proportionally increasing resonant noise. The phase shifts distribute transistor switching events across different time instances within each clock cycle, reducing the peak noise and power consumption even at elevated frequencies.
3Object-generated harmful factors
If multiple independent local clocks are used for different blocks, then resonant circuit noise is reduced, but clock drift requires inefficient rebuffering operations
Solution Approach 1:
The patent introduces phase-shifted clocks as an intermediary solution between independent local clocks and a single global clock. These phase-shifted clocks maintain synchronization relationships (avoiding drift) while distributing switching events in time (reducing noise), eliminating the need for rebuffering operations required by completely independent clocks.
Data Source
AI summary
An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.