ASRAM Test Mode Control Using Address Code Validation
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Solution Overview
Problem
Existing methods for controlling the internal test mode entry of ASRAM chips are inadequate due to the lack of extra pins and the asynchronous operation of ASRAM products, which can lead to incorrect triggering and potential chip damage from high voltages, and restrict user code usage, affecting compatibility.
Innovation Solution
A circuit comprising an address code comparator, test mode detector, test mode clock generator, and test mode decoder that uses existing pins to input a special section of codes to trigger the ASRAM chip into test mode, ensuring correct validation and reducing the risk of mis-operation by detecting consecutive falling edges and predefined validation codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If extra pins are used for test mode input/output, then test circuit control capability is improved, but device complexity and pin count increase
Solution Approach 1:
The patent applies multi-functionality by enabling existing pins (WE, OE, A0-A15) to serve both their normal operational functions and test mode entry functions. The test mode is triggered by specific code sequences on the address bus combined with normal pin signals, eliminating the need for dedicated test pins while maintaining full test capability.
Solution Approach 2:
The patent implements self-service by using the chip's own existing pins and address bus to trigger test mode without requiring external test pins or special test equipment. The normal operational signals (WE, OE, address codes) are repurposed to also serve as test mode entry commands, allowing the chip to self-test using its inherent interfaces.
2Ease of operation
If SVIH voltage is applied to trigger test mode, then test mode entry capability is improved, but risk of incorrect triggering and chip damage increases
Solution Approach 1:
The patent applies feedback by implementing a validation mechanism that checks whether the triggered test mode is legitimate before activating it. The system monitors the address bus codes and normal pin signals to verify the trigger is intentional, preventing accidental activation from glitches or misoperations while maintaining easy test mode entry through valid code sequences.
Solution Approach 2:
The patent implements preliminary action by requiring a specific code sequence on the address bus before test mode can be triggered. This preliminary validation step ensures that only intentional test mode entries are accepted, preventing incorrect triggering from voltage glitches or misoperations while maintaining the ability to easily enter test mode through proper code sequences.
3Reliability
If high SVIH voltage is applied to ensure test mode entry, then test mode activation reliability is improved, but chip safety deteriorates due to proximity to breakdown voltage
Solution Approach 1:
The patent applies parameter changes by transitioning from voltage-based triggering (SVIH) to code-based triggering on the address bus. This changes the fundamental parameter from electrical voltage magnitude to digital code sequence, eliminating the need for high voltages that risk chip damage while maintaining reliable test mode activation through validated code sequences.
Solution Approach 2:
The patent converts the potential harm of high voltage into a benefit by using the address bus code sequences (which are already part of normal operation) as the trigger mechanism. This eliminates the need for harmful high SVIH voltages while maintaining reliable test mode entry, effectively converting a harmful triggering method into a safe and reliable code-based approach.
4Ease of operation
If user code usage is restricted for test mode control, then test circuit control capability is improved, but product compatibility deteriorates
Solution Approach 1:
The patent applies segmentation by separating normal operational code usage from test mode triggering. The system identifies test mode triggers as specific code sequences on the address bus that occur under particular conditions (normal pin signals), while allowing all other code sequences to function normally in user applications. This segmentation enables test mode control without restricting legitimate user code usage, maintaining full product compatibility.
Data Source
AI summary
A circuit and method for controlling internal test mode entry of an Asynchronous Static Random Access Memory (ASRAM) chip wherein the circuit includes an address code comparator for detecting whether address codes inputted via an address bus of the ASRAM chip match a predefined validation code; a test mode detector for determining whether to let the ASRAM chip enter into an internal test mode; a test mode clock generator for generating a clock signal for the test mode decoder; and a test mode decoder for generating a test control signal. The circuit of the present application uses the existing pins of the ASRAM chip to input a special section of codes to trigger the ASRAM to enter into its internal test mode, thereby reducing the difficulty of testing the products.