Static Storage TRIZ Cases
- UMA Host Memory Cache CRC Error Detection
A host control unit computes and stores redundant codes in a volatile memory cache area to facilitate data transfer between host and nonvolatile memory.
- Memory Control Circuit Unit Dummy Data Error Correction
A memory control circuit unit fills dummy data into user data to generate corrected data for rewritable non-volatile memory modules.
- Distributed Memory Repair Network for Scalable BISR
A distributed memory repair network uses sub-block controllers to generate repair vectors only for defective columns.
- Memory Cell Classification by Bit-Flip Counts for Readout Adaptation
Classifying memory cells via bit-flip counts into impairment profiles adapts readout parameters without continuous severity measurement.
- Resistor-Free Low Power Voltage Reference Circuit
A resistor-free voltage reference circuit generates stable bias currents using diode-connected transistors.
- Folded Access Line Structure for Spike Current Suppression
A folded access line structure with integrated insulating layers increases electrical resistance to suppress spike currents in memory arrays.
- Flash Memory Leakage Detection via Driving Line Floating
A leakage detecting circuit senses voltage variations on floating driving lines to isolate word line currents.
- DRAM Testing Using Hamming Distance Subspace Segmentation
A memory testing system divides DRAM space into subspaces and uses Hamming distance to identify addresses for concurrent pattern application.
- DIMM Cooling Assembly with Intermediary Heat Spreaders
Intermediary heat spreaders resolve density-temperature contradictions by conducting heat away from closely spaced DIMMs into an ambient sink.
- EEPROM Information Storage via ECC Bit Modification
Modifying EEPROM bits encodes data without extra circuitry, as error correction codes mask changes and allow extraction during reprogramming.
- Quadrant-Based ECC Matrix Steering Aliased Bits in DRAM
Segmented code matrices steer aliased bits to non-adjacent quadrants, preventing miscorrection of double bit errors into uncorrectable triple bit faults.
- Semiconductor Memory Word Line Failure Detection
Detects improper electrical coupling between closely spaced word lines by comparing test voltages to identify manufacturing defects.
- Runtime Memory Cell Row Replacement for Defect Repair
Runtime memory cell row replacement repairs defective rows during operation, preserving ECC regions and reducing crash rates.
- ASRAM Test Mode Control Using Address Code Validation
Address code comparator validates entry codes to trigger ASRAM internal test mode using existing pins.