Runtime Memory Cell Row Replacement for Defect Repair
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Solution Overview
Problem
Existing memory repair technologies, such as Post Package Repair and Adaptive DRAM Double Device Correction, face challenges in efficiently repairing defective memory rows during runtime without impacting error correction or requiring system reboot, leading to increased system crash rates and reduced reliability.
Innovation Solution
The implementation of runtime cell row replacement, which allows for the repair of defective memory rows during system operation without using ECC memory, enabling immediate repair of single rows and preserving ECC regions for error correction, thus enhancing system reliability and availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Post Package Repair is performed during system boot or reboot, then the defective row can be repaired, but the system cannot be repaired during runtime and may crash
Solution Approach 1:
The patent implements dynamic row replacement capability that can operate in two modes: boot-time mode (using BIOS to remap defective rows) and runtime mode (using memory controller to perform actual row replacement). This dynamic approach allows the system to adapt its repair mechanism based on whether it is booting or running, enabling runtime repair without compromising system reliability.
Solution Approach 2:
The patent introduces an intermediary mechanism where the memory controller acts as a mediator between the defective row and the replacement row. During runtime, the memory controller receives defective row addresses, identifies replacement rows from spare rows, and performs the actual replacement operation, enabling repair without requiring BIOS intervention or system reboot.
2Reliability
If ADDDC is used to replace faulty memory devices, then error correction is improved, but ECC memory regions are consumed and cannot be used for error correction
Solution Approach 1:
The patent segments the memory repair function from the ECC correction function. Instead of using ADDDC which replaces entire memory devices and consumes ECC regions, this patent segments repair to the row level using dedicated spare rows within the memory array. This segmentation allows ECC regions to remain dedicated to error correction while row-level replacement handles defective rows, eliminating the conflict between repair and ECC functionality.
3Speed
If soft Post Package Repair is used for quick repair, then repair speed is improved, but the repair is temporary and may not persist
Solution Approach 1:
The patent performs preliminary identification and preparation of replacement rows during system operation. The memory controller maintains a mapping structure that tracks defective rows and has pre-identified spare rows ready for replacement. When a defective row is detected, the system can immediately proceed with replacement using the pre-prepared spare row, achieving both speed and persistence without requiring system reboot.
Data Source
AI summary
Runtime memory cell row defect detection and replacement includes detecting in a memory of a computer system operating in a runtime operating system mode, a defective row of memory cells having at least one defective cell. In response to the detection of the defective row, interrupting the operating system of the computer system and, in a runtime system maintenance mode, replacing the defective row of memory cells with a spare row of memory cells as a replacement row of memory cells. Execution of the operating system is then resumed in the runtime operating system mode Other aspects and advantages are described.