Quadrant-Based ECC Matrix Steering Aliased Bits in DRAM
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Solution Overview
Problem
Traditional on-die ECC in DRAM devices faces challenges with aliasing errors due to resource limitations, particularly when correcting double bit errors, which can result in uncorrectable triple bit errors, compromising data integrity in high-speed applications.
Innovation Solution
Implementing a quadrant-based code matrix within the memory device for internal ECC, where the data word is divided into four quadrants, preventing aliasing errors by steering aliased bits to non-adjacent quadrants, thus ensuring accurate error correction and detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional on-die SEC code is used in DRAM devices, then single bit errors can be corrected, but double bit errors may be miscorrected as single bit errors creating uncorrectable triple bit errors due to aliasing
Solution Approach 1:
The code word is divided into multiple segments, and different code types are applied to different segments. Specifically, a first code ( capable of detecting and correcting single-bit errors and detecting double-bit errors) is applied to a first segment, while a second code (capable of detecting and correcting double-bit errors) is applied to a second segment. This segmentation allows the system to handle different error types appropriately without aliasing errors propagating across the entire code word.
Solution Approach 2:
Different error correction capabilities are applied locally to different segments of the code word based on their specific error protection needs. The first segment uses a code optimized for single-bit correction with double-bit detection, while the second segment uses a code optimized for double-bit correction. This local differentiation ensures that each segment receives the appropriate level of error protection without compromising other segments.
2Reliability
If stronger error correction codes are implemented, then better error detection and correction is achieved, but computation time and resources increase
Solution Approach 1:
The code word is divided into multiple segments, and different code types are applied to different segments. Specifically, a first code ( capable of detecting and correcting single-bit errors and detecting double-bit errors) is applied to a first segment, while a second code (capable of detecting and correcting double-bit errors) is applied to a second segment. This segmentation allows the system to handle different error types appropriately without aliasing errors propagating across the entire code word.
Solution Approach 2:
Different error correction capabilities are applied locally to different segments of the code word based on their specific error protection needs. The first segment uses a code optimized for single-bit correction with double-bit detection, while the second segment uses a code optimized for double-bit correction. This local differentiation ensures that each segment receives the appropriate level of error protection without compromising other segments.
Data Source
AI summary
A memory device is configured to provide internal or on-die ECC (error checking and correction or error correction coding). In such a system, the code matrix can be managed as four quadrants of (N/4) bits, with two adjacent quadrants in an (N/2)-bit segment or portion. The N codes of the matrix correspond to the N bits of a data word to be protected by the ECC. The code matrix includes M codes corresponding to the M ECC check bits. The memory device includes internal ECC circuitry to perform ECC in the DRAM device with the ECC bits and code matrix in response to a request to access the data word. The codes in a quadrant steer an aliased bit to a quadrant other than an adjacent quadrant.