Folded Access Line Structure for Spike Current Suppression
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Solution Overview
Problem
Current memory devices face issues with spike current suppression in memory arrays, particularly in cross-point architectures, where current discharges through memory cells can result in damaging current spikes due to parasitic capacitances.
Innovation Solution
The implementation of a folded access line structure with top and bottom insulating layers increases the resistance of the electrical path to near memory cells, effectively suppressing spike currents by lengthening the discharge path and reducing current magnitude.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional access line structure is used, then the device complexity is low, but spike currents occur due to parasitic capacitances causing memory cell damage
Solution Approach 1:
The access line is divided into multiple segments with insulating layers positioned at specific locations. This segmentation creates separate electrical paths that isolate parasitic capacitances, preventing spike currents from reaching memory cells while maintaining a relatively simple overall structure.
Solution Approach 2:
Insulating layers are introduced as intermediary elements between the access line and memory cells. These layers act as mediators that block harmful electrical discharge paths caused by parasitic capacitances, thereby protecting memory cells without requiring complete structural redesign.
2Reliability
If the access line structure is modified to suppress spike currents, then the reliability improves, but the manufacturing process becomes more complex
Solution Approach 1:
The access line fabrication process is segmented into distinct stages, with insulating layers formed at specific intervals during the manufacturing sequence. This allows each segment to be processed independently using standard techniques, avoiding the need for entirely new manufacturing approaches.
Solution Approach 2:
Insulating layers are formed preliminarily during the access line fabrication process, before final memory cell assembly. This preliminary action integrates spike current suppression functionality into the base manufacturing flow, reducing the need for additional post-processing steps.
3Object-affected harmful factors
If insulating layers are added to the access line, then spike currents are suppressed, but the device complexity increases
Solution Approach 1:
Insulating layers are applied locally at specific positions along the access line where parasitic capacitances are most problematic, rather than uniformly across the entire structure. This localized approach suppresses spike currents effectively while minimizing the overall increase in device complexity.
Solution Approach 2:
The insulating layers are positioned in the vertical dimension between the access line and memory cells, creating a new spatial dimension for spike current suppression. This dimensional approach blocks harmful electrical paths without requiring horizontal expansion or lateral complexity increases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively suppresses spike currents, reducing the risk of memory cell damage and maintaining data integrity, while allowing for larger tile sizes and minimal impact on current delivery to far memory cells.
Implementation Method 1
The implementation of a folded access line structure with top and bottom insulating layers increases the resistance of the electrical path to near memory cells, effectively suppressing spike currents by lengthening the discharge path and reducing current magnitude
Data Source
AI summary
Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Spike current suppression is implemented using a folded access line structure. Each access line includes integrated top and bottom insulating layers that restrict current flow to the memory cells through a narrower middle portion of the access line. For near memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the meandering, folded circuit path that flows through the middle portion. Spike discharge that occurs when the memory cell is selected is reduced by this higher resistance path.