Memory Cell Classification by Bit-Flip Counts for Readout Adaptation

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Solution Overview

Problem

Non-volatile memory cells suffer from impairments such as read disturb, retention, and endurance, which degrade their performance and lead to read errors and potential data loss, as existing methods fail to accurately adjust readout parameters to compensate for these impairments without continuous measurement of severity levels.

Innovation Solution

A storage apparatus and method that classify memory cells into predefined impairment profiles based on bit-flip counts, allowing for the adaptation of readout parameters to optimize read performance by mapping sets of bit-flip counts to respective impairment profiles, thereby estimating individual severity levels and setting optimal read thresholds without tracking individual impairments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If readout parameters are adjusted to compensate for impairments, then readout performance is improved, but continuous measurement of severity levels is required which increases system complexity

Engineering Contradiction:
Improvereadout performanceVSAvoidcontinuous measurement requirement
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-defining multiple impairment profiles that represent different severity levels of read disturb, retention, and endurance impairments. Instead of continuously measuring impairment severity levels during operation, the system performs preliminary classification of memory cells into these predefined profiles based on initial characterization. This allows readout parameters to be adjusted according to the classified profile without requiring continuous measurement, thereby improving readout performance while reducing system complexity.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If memory cells are classified to multiple impairment profiles, then readout parameter optimization is achieved, but mapping and classification processes increase processing complexity

Engineering Contradiction:
Improvereadout parameter optimizationVSAvoidmapping and classification process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by using bit-flip counts as observable parameters to classify memory cells into different impairment profiles. The system counts the number of bit flips in read data and uses these counts as the basis for mapping cells to appropriate impairment profiles. This approach transforms the complex task of characterizing multiple impairment types into a simpler parameter-based classification system, achieving readout parameter optimization without excessive processing complexity.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If bit-flip counts are used for classification, then impairment severity estimation is achieved, but read errors may occur during classification process

Engineering Contradiction:
Improveimpairment severity estimationVSAvoidread errors during classification
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies feedback by using the observed bit-flip counts from read operations to refine and update the mapping between bit-flip patterns and impairment profiles. The system monitors bit-flip occurrences during classification and uses this feedback to improve the accuracy of impairment severity estimation. This feedback mechanism allows the system to distinguish between bit flips caused by impairments versus those occurring during the classification process itself, thereby achieving precise impairment estimation while maintaining reliability.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10438683B2Classifying memory cells to multiple impairment profiles based on readout bit-flip counts
Publication Date: 2019.10.08 APPLE INC
  • US10438683B2 patent drawing
  • US10438683B2 patent drawing
  • US10438683B2 patent drawing

AI summary

A storage apparatus includes a plurality of memory cells and storage circuitry. The storage circuitry is configured to store a mapping that maps sets of readout bit-flip counts to respective predefined impairment profiles. The impairment profiles specify two or more severity levels of respective impairment types, including read disturb, retention and endurance. Each of the bit-flip counts includes a one-to-zero error count or a zero-to-one error count. The storage circuitry is configured to read data from a group of the memory cells using given readout parameters, to evaluate an actual set of bit-flip counts corresponding to the read data, to classify the group of the memory cells to a respective impairment profile by mapping the actual set of the bit-flip counts using the mapping, and to adapt the readout parameters based on the impairment profile to which the group of the memory cells was classified.