UMA Host Memory Cache CRC Error Detection
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Solution Overview
Problem
In Unified Memory Architecture (UMA) systems, there is a need for efficient data transfer and error detection mechanisms between a host and a memory system, particularly in scenarios where data is cached and transferred between volatile and nonvolatile memory areas, to ensure data integrity and manage memory resources effectively.
Innovation Solution
The implementation of a host and memory system architecture that includes a volatile memory with a cache area, a first host control unit for computing and storing redundant codes, and a second host control unit for error detection and data transfer, utilizing CRC codes for error detection and management, with DMACs and CRC generators/detectors to facilitate command and data transfer between the host and memory system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between host and memory system in UMA architecture, then data transfer efficiency is improved, but error detection capability deteriorates
Solution Approach 1:
The patent applies preliminary action by computing CRC codes in advance before data transfer occurs. The first host control unit computes a first code (CRC) for data to be written to the device area, and the second host control unit reads a second code (CRC) before transferring data back from the device area. This preliminary error code computation and verification ensures data integrity is established before transfer operations begin, resolving the contradiction between transfer efficiency and error detection capability.
2Speed
If volatile memory is used as cache area for nonvolatile memory, then data access speed is improved, but data integrity reliability deteriorates
Solution Approach 1:
The patent implements feedback mechanisms where the second host control unit reads error codes (CRC) from the device area and performs error detection on transferred data. This feedback loop verifies data integrity after transfer operations, allowing the system to maintain the speed benefits of volatile memory caching while ensuring data integrity through post-transfer verification and error detection feedback.
3Reliability
If redundant codes are stored with data in device area, then error detection capability is improved, but memory space utilization deteriorates
Solution Approach 1:
The patent applies local quality by storing error codes (CRC) specifically in the device area of the volatile memory, which is the localized region used for caching nonvolatile memory data. This targeted approach ensures error detection capability is enhanced precisely where data caching occurs, while minimizing the impact on overall memory space utilization by confining redundant code storage to the necessary device area rather than expanding it system-wide.
Data Source
AI summary
According to one embodiment, an information processing apparatus includes a host and a memory system. The memory system includes a nonvolatile memory. The host includes a volatile memory, a first host control unit, and a second host control unit. The volatile memory includes a first area to be used by the host and a second area as a cache memory to temporarily store data of the nonvolatile memory. The first host control unit computes a first code, and stores the first data and the first code in the second area. The first code is redundant information of the first data. The second host control unit reads second data and a second code from the second area, performs error detection on the second data based on the second code, and transfers the second data. The second code is redundant information of the second data.