Assertion-Based Deadlock Detection in Hardware Design
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Solution Overview
Problem
Current hardware design verification methods, particularly simulation-based verification, are inefficient in detecting deadlocks, as they often identify deadlocks only at the end of simulation, making it difficult to pinpoint the source and requiring extensive resources and time for exhaustive state analysis.
Innovation Solution
The method involves identifying key control signals in hardware designs, generating state machines to track their states, and using assertions to detect deadlock states, with the option to apply fairness constraints for more accurate detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simulation based verification is used to detect deadlock, then the verification can be performed on the hardware design, but the deadlock is not identified until the end of simulation which makes it difficult to identify the source
Solution Approach 1:
The patent applies preliminary action by generating state machines and assertions for control signals before the actual verification process. The state machines are constructed to track control signal states, and assertions are pre-configured to detect deadlock conditions. This allows deadlock to be detected as soon as it occurs during simulation, rather than waiting until the end, because the detection mechanism is already in place and actively monitoring the design behavior.
Solution Approach 2:
The patent introduces state machines as intermediary components that mediate between the hardware design under verification and the verification process. These state machines track the states of control signals and provide this information to assertions, which then determine whether deadlock conditions exist. This intermediary layer enables continuous monitoring and immediate deadlock detection without requiring exhaustive simulation completion.
2Reliability
If exhaustive state analysis is performed to detect deadlock, then all deadlocks can be identified, but it takes a significant amount of time and resources to complete
Solution Approach 1:
The patent applies segmentation by dividing the verification task into separate state machines, each dedicated to tracking a specific control signal. Instead of analyzing all states of the entire hardware design exhaustively, the verification is segmented into multiple focused state machine analyses. Each state machine monitors its assigned control signal independently, and assertions evaluate deadlock conditions for that specific signal. This segmentation maintains thorough deadlock detection capability while significantly improving verification efficiency by avoiding the computational burden of exhaustive global state analysis.
3Loss of information
If simulation based verification with scoreboards and monitors is used, then the global end-to-end behavior can be tracked, but deadlock is discovered only at the end of simulation when all tests have been completed
Solution Approach 1:
The patent replaces the mechanical scoreboard and monitor system with a more sophisticated verification mechanism based on state machines and formal assertions. Instead of relying on scoreboards to track transactions and monitors to detect deadlocks only after simulation completion, the new system uses state machines to continuously monitor control signal states and assertions to formally verify deadlock-free operation in real-time. This substitution enables immediate deadlock detection and source identification during simulation execution, eliminating the delay inherent in traditional scoreboard-based approaches.
Data Source
AI summary
Methods and systems for detecting deadlock in a hardware design. The method comprises identifying one or more control signals in the hardware design; generating a state machine for each of the one or more control signals to track the state of the control signal; generating one or more assertions for each control signal to detect that the control signal is in a deadlock state from the state machine; and detecting whether any of the one or more control signal are in a deadlock state using the assertions. The method may also comprise generating one or more fairness constraints to impose on a particular assertion and detecting the particular control signal is in the deadlock state using the assertions under the fairness constraints.