Automated Assertion Generation for Semiconductor Verification
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Solution Overview
Problem
Conventional assertion verification technologies face challenges in ensuring high reliability and efficiency due to potential mistakes in manual assertion description, lack of confirmation of matching circuit specifications with assertion descriptions, and difficulties in describing complex state transitions, leading to incomplete verification and system revisions.
Innovation Solution
An assertion generating system that automatically converts circuit specifications into assertion descriptions using visual state transition figures, timing charts, and process sequence charts, reducing debugging work and ensuring comprehensive path coverage through graphical editing and data extraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual assertion description is used for verification, then verification can be performed, but mistakes in assertion description occur and verification reliability decreases
Solution Approach 1:
The system automatically generates assertion descriptions from circuit specifications without requiring manual intervention. The assertion description is self-generated based on the circuit design data, eliminating human errors in manual description while maintaining verification reliability.
Solution Approach 2:
The patent replaces manual mechanical writing of assertion descriptions with an automated computer-based generation system. The system extracts assertion descriptions from circuit specifications through automated processing, substituting human manual operations with computational mechanisms.
2Productivity
If manual conversion of circuit specifications to assertion descriptions is performed, then verification can be conducted, but debugging work increases and efficiency decreases
Solution Approach 1:
The system performs preliminary automated extraction and generation of assertion descriptions from circuit specifications before the verification process begins. This preliminary action eliminates the need for manual conversion and reduces subsequent debugging work by ensuring assertions are pre-generated accurately.
Solution Approach 2:
The patent replaces manual mechanical conversion processes with automated computer-based extraction and generation mechanisms, significantly reducing the time and effort required for assertion description creation and associated debugging activities.
3Reliability
If complex state transitions are described manually, then verification can be performed, but difficulty in describing increases and verification completeness decreases
Solution Approach 1:
The system automatically generates assertion descriptions for complex state transitions from circuit specifications without requiring manual description. The automated generation process handles complex transitions systematically, ensuring completeness while reducing the complexity burden on the user.
Solution Approach 2:
The patent segments the complex state transition description process into automated steps: extraction from circuit specifications, processing through generation algorithms, and output as verified assertions. This segmentation transforms complex manual tasks into manageable automated operations.
4Reliability
If comprehensive path coverage is achieved through manual testing, then verification accuracy improves, but verification time increases and productivity decreases
Solution Approach 1:
The patent replaces manual mechanical testing processes with automated computer-based verification systems that can comprehensively test all paths and sequences. The automated system achieves comprehensive path coverage faster and more efficiently than manual testing while maintaining high verification accuracy.
Solution Approach 2:
The system enables continuous automated verification of all circuit paths and sequences without interruption. The automated process can systematically explore all possible paths continuously, achieving comprehensive coverage more efficiently than intermittent manual testing while maintaining consistent verification accuracy.
Data Source
AI summary
An assertion generating system is disclosed. In an assertion generating system 207, a graphical editor 201 generates design data of a semiconductor integrated circuit by graphically editing a specification (finite state machine, process sequence) of the semiconductor integrated circuit with the use of a state transition table and a state transition figure or by editing the process sequence into a timing chart and a time series figure based on user operations, and a syntax analyzer 203 and a property extractor 204 generate a property that verifies the specification of the semiconductor integrated circuit based on the design data. The assertion generator 205 converts the property into an assertion description language 206.