Assist Gate Transistor Layout for Fin-Type Memory Integration
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Solution Overview
Problem
The integration of nonvolatile semiconductor memory devices is limited due to the difficulty in reducing the distance between fin type stacked layer structures while maintaining the reliability of assist gate electrodes, leading to residue issues during patterning, which affects the selection of memory strings and overall device performance.
Innovation Solution
The proposed solution involves a specific layout of assist gate transistors with double and single gate structures, allowing for the removal of conductive material between fin type stacked layer structures without residue, ensuring reliable operation even at reduced spacings, and utilizing the fringe effect to create normally-on channels without impurity regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between fin type stacked layer structures is reduced to enhance integration, then integration density is improved, but residue issues occur during assist gate electrode patterning
Solution Approach 1:
The assist gate transistor is divided into multiple segments: a first assist gate transistor for selecting fin type stacked layer structures, and a second assist gate transistor for selecting memory strings. This segmentation allows independent optimization of each transistor's layout and spacing requirements
Solution Approach 2:
The patent transitions from planar patterning to three-dimensional stacked structures. Fin type stacked layer structures are formed vertically, and assist gate transistors are positioned in different spatial layers, utilizing the third dimension to resolve spacing conflicts that would exist in two-dimensional patterning
2Reliability
If assist gate electrodes are separated for independent operation, then selection reliability is improved, but the distance between fin type stacked layer structures must be increased
Solution Approach 1:
Multiple fin type stacked layer structures are connected to a common beam structure, merging their support and selection functions. The assist gate transistors share common electrical connections and control signals, allowing reliable independent operation without requiring increased physical spacing between structures
Solution Approach 2:
The beam structure serves as an intermediary element that connects multiple fin type stacked layer structures. It provides mechanical support and electrical connectivity, enabling the assist gate transistors to control multiple structures without direct contact between them, thus maintaining small spacing while ensuring reliable selection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density of nonvolatile semiconductor memory devices by ensuring accurate selection of memory strings and improving reliability by eliminating residue issues during patterning, thereby supporting higher integration capacities.
Implementation Method 1
utilizing the fringe effect to create normally-on channels without impurity regions
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.