Transistor TRIZ Cases

Differentiated interface film structures balance NMOS and PMOS performance by reducing gate leakage current while maintaining inversion-layer thickness.

Delta-doped layers reduce external resistance in group III-V transistors without increasing off-state leakage current.

Epitaxial wrap-around source-drain regions reduce parasitic capacitance and contact resistance by extending laterally beyond the gate structure.

A non-oxidizing furnace anneal with controlled ramp rates reduces slip dislocation density below 5 cm−2, preventing junction leakage in isolated trenches.

A semiconductor layout uses dummy component regions to measure overlapping states between active areas and components.

A metal nitride barrier layer blocks metallic diffusion into the gate insulator, eliminating Fermi level pinning and threshold voltage variations.

An asymmetric double-gate structure reduces switching loss while maintaining withstand voltage against bidirectional stress.

Adding counter-balancing capacitances equalizes drain-to-body and source-to-body asymmetry, reducing second-order harmonic distortion in RF signals.

A solid-state imaging device structure creates a controlled overflow path for surplus electrons.

Back gate structure with inorganic and organic insulating films controls threshold voltage in oxide semiconductor devices.

Coplanar digit line and storage node contacts formed by intersecting buried word lines resolve alignment issues in highly integrated DRAM cells.

An integrated packaging structure merges two MOSFET dies into a single body with direct source and gate connection elements.

Segmented oxide semiconductor layer minimizes parasitic capacitance to resolve flickers and vertical crosstalk in LCD displays.

Surface modification protects the oxide semiconductor from etchant damage during patterning, eliminating the need for an etch-stopper layer.

Threshold voltage detection avoids false triggering during rapid power-on and SSO events.

Separating photodiodes from amplifier circuitries in a vertical stack maximizes optical fill factor while suppressing signal noise.

Non-stoichiometric MoOy reduces light absorption loss and carrier recombination at the interface, improving open-circuit voltage.

A diluted buried drift layer with monotonically increasing stripe widths modifies the electric field distribution in multi-finger lateral transistors.

Gate last process forms fin and pillar semiconductor layers using two masks, suppressing leak current by preventing partial metal filling in gate structures.

Segmented assist gate transistors remove conductive material between stacked fins, resolving patterning residue issues that limit integration density.

Merges three-terminal level-shifters with power transistors to eliminate external protection components and lower driver IC costs.

A buried cross-couple interconnect links transistor gates and source-drain regions vertically beneath the active layer.

Epitaxially growing rare earth oxide spacers reduces device footprint while maintaining spacer uniformity.

A vertical transistor array fabrication method uses sacrificial pillars to form self-aligned metal plugs for stable memory cell construction.

A nanowire memory cell uses a vertical trench and wrap-around control gate to enhance electrostatic coupling efficiency.

Homogeneous dual photodiodes share readout electronics, resolving device complexity while maintaining measurement precision for high dynamic range imaging.

Protruding gate insulating film prevents metal diffusion during siliciding, maintaining stable threshold voltage and preventing leakage.

Replacing polycrystalline substrates with mono-crystalline silicon reduces defect density and charge carrier traps in the dielectric interface.

Epitaxial growth forms monocrystalline channels in stacked memory cells, resolving the trade-off between carrier mobility and gate length control.

Composite transparent conductive and metal layers in the electrode structure reduce signal delay while enabling large-scale manufacturing.

Lattice mismatch induces strain in III-V channels, shifting energy bands to tune threshold voltages without complex doping processes.

Reduced off-current switching transistors stabilize storage capacitor charge at 1-10 Hz frame rates, suppressing flicker and lowering power consumption.

A heating method uses hydrogen gas to protect germanium films during high-temperature processing.

Elevated source/drain regions in CMOS active pixel sensors prevent silicon loss during contact etching, reducing leakage from 0.1 pA to tens of fA.

Surrounding nanowire channels with epitaxial film contacts reduces parasitic resistance, improving performance despite miniaturization.

Air gaps between gate structures allow uniform etchant access, resolving uneven etching across varying channel widths.

Replacing thick organic insulating layers with thin inorganic alternatives reduces contact hole depth, preventing light leaks and improving display efficiency.

A gate structure with a distant low-concentration doped region shunts current to reduce trigger voltage.

An intermediary doped well pickup region stabilizes threshold voltage by removing hot carriers from the silicon body layer, preventing programming deviations.

A vertical transistor structure with buried bit lines increases the contact region between the active pillar and the bit line.

Organic silicon source adsorption on the first electrode layer enables uniform silicon germanium deposition for metal-insulator-metal capacitors.

Overlapping vertical steering diodes with a main Zener diode reduces capacitance by 70% while maintaining transient voltage suppression.

A second dielectric spacer deposits between metal gates to increase electrical isolation in high voltage FinFETs.

A multilayer connection structure uses dielectric sidewall spacers to isolate electrical conductors in a three-dimensional stacked IC device.

A spacer etching process forms ultra-narrow insulated gates using conformal film deposition and selective removal.

Stacking vertical transistors above horizontal ones increases SRAM integration density while reducing mask count.

A semiconductor driving device uses signal level encoding to identify abnormal causes and their continuation.

A semiconductor device reorients a contact plug perpendicular to a gate trench to secure its longer-side dimension.

Varying gate contact widths across device and field regions reduces area while maintaining reliability through local quality principles.

A cyclic etch process defines semiconductor fins using alternating polymer deposition and removal phases.