FET Second Harmonic Distortion Reduction via Capacitance Balancing
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Solution Overview
Problem
Conventional MOSFETs operating in the accumulated charge regime exhibit undesirable non-linear characteristics, particularly second-order harmonic distortion, which adversely affects the performance of RF signals due to capacitance asymmetry between the drain and body, and source and body, leading to harmonic distortion and intermodulation distortion.
Innovation Solution
The solution involves equalizing the capacitance asymmetry between the drain-to-body and source-to-body capacitances by adding counter-balancing capacitances or using a bias voltage source to balance the charge, thereby reducing second-order harmonic distortion. This can be achieved by implementing additional capacitances as distinct capacitor structures or by rearranging the device geometry and materials to create purposeful parasitic capacitances, and optionally incorporating a body-to-gate diode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a body-to-gate diode is added to reduce harmonic distortion, then intermodulation distortion is reduced, but second-order harmonics remain and device complexity increases
Solution Approach 1:
A capacitor is introduced as an intermediary element connected between the body and source/drain terminals. This capacitor mediates the charge accumulation process by providing a controlled path for charge redistribution, thereby reducing second-order harmonics without requiring a body-to-gate diode connection.
Solution Approach 2:
The invention changes the electrical parameters of the FET by introducing a capacitor that modifies the charge accumulation characteristics. By adjusting the capacitor value, the charge accumulation is controlled to reduce second-order harmonics while maintaining the body-to-gate diode connection for intermodulation distortion reduction.
2Object-generated harmful factors
If counter-balancing capacitances are added to equalize drain-to-body and source-to-body capacitances, then second-order harmonic distortion is reduced, but device complexity increases
Solution Approach 1:
The invention intentionally introduces asymmetry in the form of counter-balancing capacitances connected to the body terminal. These capacitances are designed to compensate for the inherent asymmetry in drain-to-body and source-to-body capacitances, thereby equalizing the total capacitance values and reducing second-order harmonic distortion.
Solution Approach 2:
By adding counter-balancing capacitances, the electrical parameters (capacitance values) are modified to achieve equality between drain-to-body and source-to-body total capacitances. This parameter change directly addresses the capacitance asymmetry that causes second-order harmonics.
3Device complexity
If the capacitance asymmetry between drain-to-body and source-to-body is not equalized, then device structure remains simple, but second-order harmonic distortion increases
Solution Approach 1:
A capacitor serves as an intermediary element that equalizes the capacitance asymmetry without requiring complex structural modifications. The capacitor is connected between the body and source/drain terminals, providing a simple yet effective means to balance the total capacitances and reduce second-order harmonics.
Solution Approach 2:
The invention changes the electrical parameters by introducing capacitance elements that modify the total drain-to-body and source-to-body capacitances. By carefully selecting the capacitor values, the asymmetry is compensated, achieving parameter equality without complex structural changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces second-order harmonic distortion in FETs used for RF signals, improving harmonic characteristics without compromising power handling or introducing adverse effects on other harmonic frequencies, as demonstrated by reduced second harmonic values at specific voltage conditions.
Implementation Method 1
when a voltage is applied between the gate G and source S terminals of a FET, a generated electric field penetrates through the gate oxide to the transistor body B
Implementation Method 2
when the FET is switched to an OFF-state with a nonzero gate bias voltage applied with respect to the source S and drain D, an accumulated charge may occur under the gate G
Implementation Method 3
the asymmetry of the drain-to-body capacitance Cdb and source-to-body capacitance Csb is equalized by adding at least one of a counter-balancing capacitance C1 between the source S and the body B or a counter-balancing capacitance C2 between the drain D and the body B
Data Source
AI summary
A structure and method for reducing second-order harmonic distortion in FET devices used in applications that are sensitive to such distortion, such as switching RF signals. The asymmetry of the drain-to-body capacitance Cdb and source-to-body capacitance Csb of a FET device are equalized by adding offsetting capacitance or a compensating voltage source.