SOI Non-Volatile Memory Threshold Voltage Stabilization
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Solution Overview
Problem
In non-volatile memory devices on silicon on insulation (SOI) substrates, the accumulation of hot carriers at the silicon body layer causes variations in the threshold voltage, affecting programming operations.
Innovation Solution
A doped region, or well pickup region, is electrically connected to the silicon body layer beneath the gate of the memory cell, allowing for the application of voltage to maintain the threshold voltage and prevent deviations due to hot carrier accumulation, using configurations such as a T-shaped gate and doped regions in the silicon body layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a non-volatile memory device is fabricated on an SOI substrate without additional doped regions, then the device structure is simpler, but the threshold voltage varies due to hot carrier accumulation at the silicon body layer
Solution Approach 1:
A well pickup region (additional doped region) is introduced as an intermediary component between the silicon body layer and the hot carriers. This well pickup region captures and removes hot carriers that accumulate during operation, thereby stabilizing the threshold voltage without fundamentally changing the overall memory device architecture
Solution Approach 2:
The additional doped region is selectively positioned at specific locations beneath the gate and selecting transistor gates where hot carrier accumulation occurs. By applying local quality enhancement only where needed, the solution maintains threshold voltage stability without unnecessarily increasing overall device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains the threshold voltage of the memory cell, enhancing operation efficiency by preventing voltage deviations from hot carrier accumulation, thereby improving programming and erasing operations.
Implementation Method 1
the first conductive type doped region is disposed in the first conductive type silicon body layer and is electrically connected to the first conductive type silicon body layer beneath the gate
Data Source
AI summary
A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.