Wrap-Around Source-Drain Regions for ETSOI Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with extremely thin semiconductor-on-insulator (ETSOI) channels, existing methods for forming source and drain regions result in high parasitic capacitance due to thick S/D epitaxy, which increases resistance and contact resistance, making it challenging to achieve low contact resistance and sharp junctions.
Innovation Solution
The formation of wrap-around source and drain regions around the semiconductor layer, with epitaxial growth on both sides of the gate structure and in undercuts of the buried dielectric layer, reduces the height of the S/D regions below the gate, increasing dopant volume and reducing parasitic capacitance, while contacts are formed on top and sides to further lower contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If thick S/D epitaxy is used to ensure sufficient dopants, then dopant volume is increased, but parasitic capacitance between gate and S/D epitaxy increases
Solution Approach 1:
The source and drain regions are formed to wrap around the semiconductor layer in three dimensions, extending laterally beyond the gate structure and underneath the gate. This spatial redistribution allows sufficient dopant volume to be achieved through lateral and vertical extension rather than increasing thickness above the gate, thereby reducing gate-to-S/D overlap capacitance while maintaining adequate dopant quantity for low contact resistance
Solution Approach 2:
The S/D regions are segmented into multiple portions: a first portion formed on the semiconductor layer adjacent to the gate structure, a second portion formed underneath the gate structure, and extensions lateral to the gate. This segmentation allows each portion to contribute to dopant volume while minimizing the height of material above the channel, reducing parasitic capacitance
2Quantity of substance
If thick S/D epitaxy is formed above the channel region, then sufficient dopants are present, but gate to S/D overlap capacitance increases
Solution Approach 1:
The S/D regions extend in multiple dimensions: laterally beyond the gate structure boundaries and vertically underneath the gate structure. This multi-dimensional positioning ensures sufficient dopant volume is achieved through spatial distribution rather than increasing the height of material above the channel, thereby minimizing gate-to-S/D overlap capacitance while maintaining adequate dopant amount for low contact resistance
3Ease of manufacture
If conventional S/D regions are formed, then manufacturing is simpler, but contact resistance is high
Solution Approach 1:
The S/D regions are segmented into multiple portions including a first portion adjacent to the gate structure, a second portion underneath the gate structure, and lateral extensions. This segmentation increases the total contact area between the S/D regions and the semiconductor layer, providing multiple pathways for current flow and thereby reducing contact resistance while remaining achievable through standard epitaxial growth and etching processes
Solution Approach 2:
The S/D regions are formed to wrap around the semiconductor layer, with portions positioned underneath the gate structure and lateral extensions wrapping around the ends of the semiconductor layer. This wrap-around configuration maximizes the contact area between S/D regions and the semiconductor layer, providing extensive dopant supply and low contact resistance through a configuration that integrates with the existing gate structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and contact resistance, enhancing the performance of ETSOI devices by increasing dopant volume and achieving sharp junctions, leading to improved device performance with reduced overlap capacitances and lower contact resistance.
Implementation Method 1
epitaxially growing source and drain regions wrapped around the semiconductor layer by forming the source and drain regions adjacent to the gate structure on a first side of the semiconductor layer
Data Source
AI summary
A method for forming a semiconductor device includes etching a semiconductor layer using a gate structure and spacers as a mask to protect portions of the semiconductor layer that extend beyond the gate structure. Undercuts are formed in a buried dielectric layer under the gate structure. Source and drain regions are epitaxially growing and wrapped around the semiconductor layer by forming the source and drain regions adjacent to the gate structure on a first side of the semiconductor layer and in the undercuts on a second side of the semiconductor layer opposite the first side.