Integrated MOSFET Packaging Structure for Conductive Loss Reduction

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Solution Overview

Problem

Conventional semiconductor packaging structures for power transistors result in significant conductive loss and occupy large footprint when integrating multiple MOSFET ICs, limiting the miniaturization of packaging substrates.

Innovation Solution

An integrated packaging structure that combines two MOSFET dies into a single package, utilizing source and gate connection elements to reduce conductive path length and substrate size, with the option of arranging gate electrode pads at corners for increased layout flexibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If two MOSFET ICs are separately packaged and connected by conductive wires, then each IC can be independently manufactured and tested, but the conductive path becomes long resulting in greater conductive loss and the packaging footprint increases

Engineering Contradiction:
Improveconductive lossVSAvoidpackaging footprint
Core Design Contradiction:
Loss of energyVSArea of stationary object

Solution Approach 1:

The patent merges two separately packaged MOSFET ICs into a single integrated packaging structure. The first and second MOSFET dies are mounted on the same packaging substrate with their respective connection elements (first source connection element, second source connection element, first gate connection element, second gate connection element) directly connecting to corresponding regions on the packaging substrate. This integration eliminates the need for long external conductive wires, thereby reducing conductive loss and minimizing the packaging footprint.

Inventive Principle:
Principle #5Merging (Combining)

2Ease of manufacture

If two MOSFET ICs are separately packaged, then manufacturing and testing can be performed independently on each IC, but the overall packaging structure occupies significant space limiting substrate miniaturization

Engineering Contradiction:
Improveindependent manufacturing and testingVSAvoidpackaging substrate size
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The packaging substrate is segmented into distinct functional regions: a first setting region for mounting the first MOSFET die and a second setting region for mounting the second MOSFET die. Each die has its own dedicated connection elements (source and gate connection elements) that connect to corresponding regions on the substrate. This segmentation allows independent manufacturing and testing of each die while maintaining a compact integrated structure that minimizes overall substrate size.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If conventional separate packaging with conductive wires is used, then design flexibility is maintained, but the long conductive path results in significant energy loss

Engineering Contradiction:
Improvedesign flexibilityVSAvoidconductive loss
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The packaging substrate acts as an intermediary structure that directly connects the source and gate regions of both MOSFET dies through integrated connection elements. Instead of using long external conductive wires, the connection elements (first source connection element, second source connection element, first gate connection element, second gate connection element) are formed as part of the substrate structure, providing short direct pathways for current flow. This intermediary structure maintains design flexibility while dramatically reducing conductive loss.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10090298B2Integrated packaging structure
Publication Date: 2018.10.02 TAIWAN SEMICONDUCTOR CO LTD
  • US10090298B2 patent drawing
  • US10090298B2 patent drawing
  • US10090298B2 patent drawing

AI summary

An integrated packaging structure is provided. In the package structure, an integrated component body has a first source region, a second source region, a first setting region, and a second setting region, which are separated from each other. A first MOSFET die and a second MOSFET die are located on the first setting region and the second setting region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed from the top surface and spaced apart from each other. A first source connection element is connected to the source electrode pad of the first MOSFET die and the first source region. A second source connection element is connected to the source electrode pad of the second MOSFET die and the second source region. A gate connection element is connected to the gate electrode pad and a gate region of the integrated component body.