Vertical Transistor Cell Area Reduction via Buried Bit Line
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Solution Overview
Problem
Conventional semiconductor devices with horizontal transistors occupy large areas due to their structure, making it difficult to reduce the overall size of semiconductor memory devices, and existing methods to address this issue are limited in effectively reducing cell area and improving drive current.
Innovation Solution
The use of a vertical transistor structure with an active pillar protruded from a semiconductor substrate, featuring recesses for burying bit lines and word lines, which increases the contact region between the bit line and active region, thereby reducing cell area and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional planar transistor with horizontal channel region is used, then the transistor structure is simple to manufacture, but the semiconductor device occupies a large area
Solution Approach 1:
The patent transitions from a conventional planar transistor with horizontal channel region to a vertical transistor with vertical channel region extending in the third dimension (depth). The active region forms a vertical pillar structure with the channel extending from the substrate surface downward, utilizing vertical space rather than horizontal plane area, thereby significantly reducing the footprint of the semiconductor device while maintaining transistor functionality
2Power
If the contact region between bit line and active region is increased, then drive current is enhanced, but fabrication process becomes more complex
Solution Approach 1:
The patent performs preliminary actions during the formation of the vertical active region and recess structures. The recess is formed in the active region before bit line deposition, pre-positioning the contact interface. The bit line is then deposited to fill the recess, automatically achieving optimal contact area between the bit line and active region without requiring additional complex fabrication steps to increase contact region
Data Source
AI summary
A semiconductor device including a vertical transistor and a method for forming the same are disclosed, which can greatly reduce a cell area as compared to a conventional layout of 8F2 and 6F2, and need not form a bit line contact, a storage node contact, or a land plug, such that the number of fabrication steps is reduced and a contact region between the bit line and the active region is increased in size. The semiconductor device including a vertical transistor includes an active region formed over a semiconductor substrate, a first recess formed to have a predetermined depth at both sides of the active region, and a bit line buried in the first recess.