Vertical Memory Cell Stacking with Epitaxial Channel Control
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Solution Overview
Problem
Vertical memory devices face challenges in controlling gate length, especially when using monocrystalline materials, and stacking multiple devices due to increased resistance when using polycrystalline materials.
Innovation Solution
A memory device with multiple layers of memory cells stacked on a substrate, where each cell comprises a first and second source/drain layer, a channel layer, and a storage gate stack, with the channel layer formed by epitaxial growth to control gate length, and monocrystalline semiconductor materials used to reduce resistance and improve carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a monocrystalline material is used for the channel, then carrier mobility is improved, but gate length control becomes difficult
Solution Approach 1:
The patent transitions from planar device architecture to vertical device architecture, changing the spatial dimension of device operation. In the vertical configuration, the channel extends vertically through multiple stacked layers, allowing gate length to be controlled by vertical etching depth rather than lateral lithography, thereby improving gate length control while maintaining high carrier mobility with monocrystalline materials
Solution Approach 2:
The patent divides the device into multiple stacked layers including channel layers, source/drain layers, and gate structures arranged vertically. This segmentation allows independent optimization of each layer's material properties and dimensions, enabling precise control of gate length through vertical stacking while maintaining monocrystalline channel quality
2Manufacturing precision
If a polycrystalline material is used for the channel, then gate length control is improved, but channel resistance increases greatly
Solution Approach 1:
By switching to vertical device architecture, the patent enables precise gate length control through vertical stacking and etching processes while using monocrystalline materials for the channel, thereby achieving both good gate length control and low channel resistance simultaneously
Solution Approach 2:
The patent employs composite material structures with monocrystalline semiconductor materials for the channel region to ensure low resistance and high carrier mobility, while using different materials for source/drain regions and gate structures, optimizing each component's electrical properties
3Quantity of substance
If multiple vertical devices are stacked, then storage density is improved, but total resistance becomes excessively high
Solution Approach 1:
The patent merges multiple device layers vertically with shared source/drain structures between adjacent devices. The source/drain regions extend through multiple channel layers, creating shared conductive paths that reduce the number of series resistance interfaces and lower total device resistance while maintaining high storage density through vertical stacking
Solution Approach 2:
By stacking devices vertically and sharing source/drain regions across multiple layers, the patent achieves high storage density in the vertical dimension while reducing resistance through shared horizontal conductive paths, effectively decoupling density improvement from resistance increase
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for well-controlled gate length and reduced channel resistance, enabling easy stacking of vertical devices and increasing storage density, while also saving wafer area by forming memory cells in machining holes.
Implementation Method 1
the channel layer formed by epitaxial growth to control gate length
Data Source
AI summary
The memory device includes multiple stacked layers of memory cells. Each of the layers includes a first array of first memory cells and a second array of second memory cells, which are nested with each other. The first memory cells and the second memory cells in the respective layers are substantially aligned to each other in a stacking direction of the memory cell layers. Each of the first memory cells is a vertical device based on a first source/drain layer, a channel layer, and a second source/drain layer stacked. Each of the second memory cells is a vertical device based on an active semiconductor layer extending in the stacking direction. The first and second memory cells include respective storage gate stacks, which share a common gate conductor layer. Gate conductor layers in the same memory cell layer are integral with each other.