Oxide Semiconductor TFT Array Substrate Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional array substrates for LCDs suffer from high parasitic capacitance due to overlap between gate and source/drain electrodes, leading to degraded TFT characteristics, such as flickers, vertical crosstalk, and reduced resolution, especially in compact portable terminals.
Innovation Solution
The array substrate incorporates an oxide semiconductor layer with a T-shaped or rotated-T shape structure, featuring an etch stopper that exposes three ends of the oxide semiconductor layer, allowing the source and drain electrodes to contact only specific ends, thereby reducing the overlap area and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the gate electrode and source/drain electrodes are formed with conventional overlapping structure, then the TFT switching function is achieved, but parasitic capacitance increases leading to degraded resolution and image quality
Solution Approach 1:
The oxide semiconductor layer is segmented into multiple regions with different thicknesses: a first region with greater thickness under the gate electrode for low resistance, and a second region with lesser thickness between source and drain electrodes for reduced parasitic capacitance. This segmentation allows simultaneous optimization of electrical conductivity and capacitance reduction.
Solution Approach 2:
Different regions of the oxide semiconductor layer are given different local properties: the first region has greater thickness to provide low contact resistance with source/drain electrodes, while the second region has lesser thickness to minimize parasitic capacitance with the gate electrode. This local quality differentiation resolves the contradiction between conductivity and capacitance.
2Ease of manufacture
If the oxide semiconductor layer has uniform thickness, then manufacturing is simplified, but TFT characteristics are degraded due to high parasitic capacitance and resistance
Solution Approach 1:
The oxide semiconductor layer is divided into thickness segments: a first region with greater thickness for low resistance contact, and a second region with lesser thickness for low parasitic capacitance. This can be achieved through selective etching or selective deposition processes that maintain manufacturing feasibility while improving device characteristics.
Solution Approach 2:
The oxide semiconductor layer exhibits local quality variations in thickness: thicker regions where low resistance is needed (under electrodes), and thinner regions where low capacitance is needed (between electrodes). This local differentiation improves TFT reliability without completely complicating the manufacturing process.
3Measurement precision
If the overlap area between gate and source/drain electrodes is reduced, then parasitic capacitance decreases improving resolution, but the TFT switching function may be compromised
Solution Approach 1:
The oxide semiconductor layer is segmented to provide electrical connection pathways that bypass the need for large electrode overlap. The thicker first region ensures good electrical contact between source/drain electrodes and the semiconductor channel, while the thinner second region minimizes gate-to-drain capacitance, maintaining switching function with reduced overlap.
Solution Approach 2:
Local quality variations in the oxide semiconductor layer thickness enable the TFT to maintain switching function with reduced overlap area. The thicker region ensures adequate electrical contact for switching, while the thinner region reduces parasitic capacitance, allowing the gate to effectively control the channel without requiring large overlap areas.
Data Source
AI summary
An array substrate includes a gate line on a substrate including a pixel region, the gate line extending in one direction; a gate electrode in the pixel region and extending from the gate line; a gate insulating layer on the gate line and the gate electrode; a data line on the gate insulating layer and crossing the gate line to define the pixel region; an oxide semiconductor layer on the gate insulating layer and having three ends, the oxide semiconductor layer corresponding to the gate electrode; an etch stopper on the oxide semiconductor layer to expose the three ends of the oxide semiconductor layer; a source electrode contacting two ends of the three ends of the oxide semiconductor layer and extending from the data line; and a drain electrode contacting one end of the three ends of the oxide semiconductor layer and spaced apart from the source electrode.