Nanowire Memory Cell Vertical Trench Gate Coupling
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Solution Overview
Problem
Conventional flash memory cells face challenges in scaling beyond 50 nm due to limitations in tunnel and control dielectric thickness, leading to data-retention issues, high operating voltages, and short channel effects, which hinder integration density and efficiency.
Innovation Solution
The development of a memory cell with a nanowire-based transistor configuration, where a nanowire is formed within a vertical trench and surrounded by a control gate, enabling enhanced coupling efficiency and reduced processing complexity, thus improving scaling and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar flash memory is scaled down, then integration density improves, but data retention deteriorates due to insufficient dielectric thickness
Solution Approach 1:
The patent transitions from planar 2D memory architecture to vertical 3D nanowire architecture. The nanowire extends vertically through the substrate with gate structures wrapping around it at different heights, enabling three-dimensional spatial arrangement that increases integration density while maintaining sufficient dielectric thickness for data retention.
Solution Approach 2:
The patent implements nested structures where control gates and charge storage structures are positioned concentrically around the vertical nanowire channel. The nanowire is surrounded by tunnel dielectric, charge storage structure, and control gate in nested layers, maximizing space utilization in the vertical dimension.
2Length of moving object
If dielectric thickness is reduced for scaling, then device size decreases, but operating voltage increases due to poor coupling ratio
Solution Approach 1:
The vertical nanowire configuration with wrap-around gates creates superior electrostatic coupling compared to planar structures. The gate structures surround the channel in multiple dimensions, improving the coupling ratio between gate and channel, which allows for reduced dielectric thickness without increasing operating voltage.
3Area of stationary object
If access gate length is reduced for scaling, then device area decreases, but leakage current increases due to short channel effects
Solution Approach 1:
The patent uses vertical nanowire channels with wrap-around gates that provide enhanced electrostatic control over the channel. The gates surround the channel from multiple directions, improving field effect control and reducing short channel effects, which suppresses leakage current even in scaled devices.
Solution Approach 2:
The patent employs composite material structures including vertical nanowire channels combined with wrap-around gate structures and charge storage layers. This composite architecture provides superior electrostatic control compared to conventional planar structures, reducing leakage through improved channel confinement.
4Speed
If conventional two-transistor configuration is used, then fast random access is achieved, but manufacturing complexity increases beyond 50 nm scaling
Solution Approach 1:
The patent implements a unified vertical nanowire structure that can serve multiple functions. The same vertical channel and gate structure can be used for both access transistor and memory transistor functions, reducing the number of separate components needed and simplifying manufacturing while maintaining fast access performance.
Data Source
AI summary
A memory cell, the memory cell comprising a substrate, a nanowire extending along a vertical trench formed in the substrate, a control gate surrounding the nanowire, and a charge storage structure formed between the control gate and the nanowire.