Oxide Semiconductor TFT with Composite Electrodes for Signal Delay Reduction
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Solution Overview
Problem
Current thin film transistors in liquid crystal display devices face challenges in achieving high resolution and large-scale production due to issues with mobility, uniformity, and material costs, particularly with amorphous silicon and polysilicon-based TFTs, and the use of transparent electrodes leading to increased resistance and signal delay.
Innovation Solution
A thin film transistor substrate is manufactured using a zinc oxide-based semiconductor layer with a multi-layered structure for source and drain electrodes, comprising a transparent conductive layer and a low-resistance metal layer, along with a simplified process that includes forming a gate insulating layer and oxide semiconductor pattern, and patterning conductive layers to create a second conductive pattern group, which includes data and source/drain electrodes, and a pixel electrode connected to the drain electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If transparent electrodes (ITO, Au) are used for source/drain electrodes in oxide semiconductor TFTs, then the TFT can be manufactured by low temperature process with appropriate mobility, but the resistance rises to bring about considerable signal delay when large area is covered
Solution Approach 1:
The source/drain electrodes are constructed as composite structures combining transparent conductive oxide layers (ITO, IZO) with metal layers (Al, Mo, Cu). This composite approach maintains the low-temperature manufacturing advantage of oxide semiconductors while the metal layers provide low resistance to eliminate signal delay in large-area displays.
Solution Approach 2:
The multi-layered electrode structure serves multiple functions: the transparent conductive oxide layers provide transparency and conductivity, while the metal layers provide low resistance. This multi-functional design allows the electrodes to simultaneously satisfy optical, electrical, and mechanical requirements.
2Reliability
If polysilicon is used for TFT active layer, then high mobility and constant current condition are achieved, but poor uniformity and high temperature process prevent large scale production
Solution Approach 1:
The invention changes the material parameter from polysilicon to zinc oxide-based semiconductor, which enables low-temperature processing while maintaining appropriate mobility through compositional control and optimized device structure, thus enabling large-scale production.
Solution Approach 2:
The oxide semiconductor TFT employs composite material structures including multi-layered gate electrodes and source/drain electrodes, which compensate for the lower mobility of oxide semiconductors compared to polysilicon while enabling low-temperature, large-scale manufacturing.
3Temperature
If amorphous silicon is used for TFT active layer, then low temperature manufacturing is achieved, but low mobility fails to meet constant current condition
Solution Approach 1:
The invention changes the semiconductor material from amorphous silicon to zinc oxide-based compound semiconductors, which intrinsically provide higher carrier mobility while maintaining low-temperature processing capability, thus satisfying both manufacturing and performance requirements.
4Reliability
If Au is used for source/drain electrodes, then conductivity is improved, but material cost is increased
Solution Approach 1:
The invention replaces expensive gold electrodes with cheaper metal materials such as Al, Mo, or Cu in the multi-layered electrode structure, achieving comparable or superior electrical performance at significantly reduced material cost, making large-area displays economically viable.
Data Source
Figure 1
Figure 2A
Figure 2B~2C
AI summary
A thin film transistor substrate and a method of manufacturing the same are disclosed. The method of manufacturing a thin film transistor substrate includes forming a first conductive pattern group including a gate line, a gate electrode, and a lower gate pad electrode on a substrate, forming a gate insulating layer on the substrate on which the first conductive pattern group is formed, forming an oxide semiconductor pattern overlapping the gate electrode on the gate insulating layer, and forming first and second conductive layers on the substrate on which the oxide semiconductor pattern is formed and patterning the first and second conductive layers to form a second conductive pattern group including a data line, a source electrode, a drain electrode, and a data pad.