Oxide Semiconductor TFT Array Substrate Fabrication
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Solution Overview
Problem
The existing array substrate fabrication processes for oxide semiconductor thin film transistors (TFTs) face issues such as damage to the oxide semiconductor layer due to etchant exposure and the need for additional mask processes, which increase production costs and decrease yield.
Innovation Solution
The array substrate is fabricated with an oxide semiconductor layer formed on top of the source and drain electrodes, eliminating the need for an etch-stopper and reducing the number of mask processes, and a surface modification layer is used to enhance adhesion between the oxide semiconductor layer and the metal electrodes, preventing damage and improving transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an etch-stopper layer is added to protect the oxide semiconductor layer from etchant damage, then the oxide semiconductor layer is protected from damage, but the device complexity and number of fabrication processes increase
Solution Approach 1:
A surface modification layer is introduced as an intermediary between the oxide semiconductor layer and the etchant. This modification layer (formed by plasma treatment, atomic layer deposition, or chemical treatment) provides etchant resistance without requiring a separate etch-stopper layer, thus protecting the oxide semiconductor layer while avoiding additional structural complexity
Solution Approach 2:
The surface properties of the oxide semiconductor layer are modified through plasma treatment, atomic layer deposition, or chemical treatment to enhance etchant resistance. By changing the surface parameters (hydrophobicity, surface energy, chemical composition) of the oxide semiconductor layer, it gains inherent protection against etchant damage without requiring an additional etch-stopper layer
2Reliability
If an etch-stopper layer is added to prevent oxide semiconductor layer damage, then the oxide semiconductor layer is protected, but the manufacturing cost and production time increase
Solution Approach 1:
The surface modification layer serves as a protective intermediary that can be integrated into existing fabrication processes. By using plasma treatment or atomic layer deposition steps that are already part of the manufacturing flow, the patent avoids adding separate etch-stopper deposition and removal processes, thereby maintaining production efficiency while achieving protection
Solution Approach 2:
The oxide semiconductor layer surface is pre-modified with etchant-resistant properties before the etching process. This preliminary action (plasma treatment, atomic layer deposition, or chemical treatment) ensures that the oxide semiconductor layer is already protected when etching occurs, eliminating the need for post-etching cleanup or additional protective layers, thus streamlining the production process
3Ease of manufacture
If the oxide semiconductor layer is exposed to etchant for metal layer patterning, then the metal layer can be patterned, but the oxide semiconductor layer is damaged and TFT properties are degraded
Solution Approach 1:
The surface modification layer acts as a mediator that allows etchant to selectively remove metal layers while being blocked from damaging the oxide semiconductor layer. This intermediary layer enables standard wet etching processes to be used for metal patterning without compromising the underlying oxide semiconductor layer, thus maintaining both ease of manufacture and manufacturing precision
Solution Approach 2:
The surface parameters of the oxide semiconductor layer are changed through plasma treatment, atomic layer deposition, or chemical treatment to create an etchant-resistant surface. This parameter change allows the oxide semiconductor layer to withstand standard etching conditions used for metal layer patterning, enabling easy manufacturing while preserving TFT property consistency
Data Source
AI summary
A method of manufacturing an array substrate is discussed. The method includes forming a gate line on a substrate including a pixel region, forming a gate electrode on the substrate and connected to the gate line, and forming a gate insulating layer on the gate line and the gate electrode. The method further includes forming a data line on the gate insulating layer and crossing the gate line to define the pixel region, forming a source electrode and a drain electrode on the gate insulating layer and corresponding to the gate electrode, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode, and forming an oxide semiconductor layer on top of the source and drain electrodes.